Abstract: A thin film transistor is provided, and includes a gate electrode, a first gate dielectric layer, a second gate dielectric layer, a channel layer, a source electrode and a drain electrode. The gate electrode is disposed on a substrate. The first gate dielectric layer is disposed on the gate electrode and the substrate, and has a radio of the number of silicon-hydrogen bonds to the number of nitrogen-hydrogen bonds, in which the ratio is between 0.2 and 1.0. The second gate dielectric layer is disposed on the first gate dielectric layer, and has a radio of the number of silicon-hydrogen bond to the number of nitrogen-hydrogen bonds, in which the ratio is between 0.01 and 0.2. The channel layer is disposed on the second gate dielectric layer. The source electrode and drain electrode are disposed on the channel layer and located at two opposite sides of the channel layer.

Abstract: Super-junction MOSFETs by trench fill system requires void-free filling epitaxial growth. This may require alignment of plane orientations of trenches in a given direction. Particularly, when column layout at chip corner part is bilaterally asymmetrical with a diagonal line between chip corners, equipotential lines in a blocking state are curved at corner parts due to column asymmetry at chip corner. This tends to cause points where equipotential lines become dense, which may cause breakdown voltage reduction. In the present invention, in power type semiconductor active elements such as power MOSFETs, a ring-shaped field plate is disposed in chip peripheral regions around an active cell region, etc., assuming a nearly rectangular shape. The field plate has an ohmic-contact part in at least a part of the portion along the side of the rectangle. However, in the portion corresponding to the corner part of the rectangle, an ohmic-contact part is not disposed.

Abstract: A method for forming an oxide that can be used as a semiconductor of a transistor or the like is provided. In particular, a method for forming an oxide with fewer defects such as grain boundaries is provided. One embodiment of the present invention is a semiconductor device including an oxide semiconductor, an insulator, and a conductor. The oxide semiconductor includes a region overlapping with the conductor with the insulator therebetween. The oxide semiconductor includes a crystal grain with an equivalent circle diameter of 1 nm or more and a crystal grain with an equivalent circle diameter less than 1 nm.

Abstract: An organic light emitting element is disclosed which includes: an anode and a cathode formed on a substrate and disposed to face each other; and a stack formed between the anode and the cathode and configured to include a hole transport layer, a first light emission layer, a second emission layer and an electron transport layer. The first light emission layer adjacent to the anode includes a host with band gaps of 1.00 eV˜2.70 eV and 2.76 eV˜4.00 eV. Such an organic light emitting element allows at least two light emission layers to be included into a single stack so that a driving voltage is reduced.

Abstract: Lamination transfer films and methods for transferring a structured layer to a receptor substrate. The transfer films include a carrier substrate having a releasable surface, a sacrificial template layer applied to the releasable surface of the carrier substrate and having a non-planar structured surface, and a thermally stable backfill layer applied to the non-planar structured surface of the sacrificial template layer. The sacrificial template layer is capable of being removed from the backfill layer, such as via pyrolysis, while leaving the structured surface of the backfill layer substantially intact.

Abstract: A memory device includes a capacitor, a tunneling-enhanced device, and a transistor. In accordance with an embodiment, capacitor has first and second electrodes wherein the first electrode of the capacitor serves as a control gate of the memory device. The tunneling-enhanced device has a first electrode and a second electrode, wherein the first electrode of the second capacitor serves as an erase gate of the memory device and the second electrode of the tunneling-enhanced device is coupled to the second electrode of the capacitor to form a floating gate. The transistor has a control electrode and a pair of current carrying electrodes, wherein the control electrode of the transistor is directly coupled to the floating gate. In accordance with another embodiment, a method for manufacturing the memory device includes a method for manufacturing the memory device.

Abstract: A thin film transistor includes: a gate electrode and a pair of source-drain electrodes provided on a substrate; an oxide semiconductor layer provided between the gate electrode and the pair of source-drain electrodes, the oxide semiconductor layer forming a channel; a protection film provided over whole of a surface above the substrate; and a gate insulating film provided on a gate electrode side of the oxide semiconductor layer, the gate insulating film having end faces part or all of which are covered with the pair of source-drain electrodes or with the protection film.

Abstract: A pixel structure includes a first patterned transparent conductive layer, an active layer, an insulating layer and a second patterned transparent conductive layer. The first patterned transparent conductive layer is disposed on a substrate and includes a source, a drain and a pixel electrode connected to the drain. The active layer connects the source and the drain. The insulating layer covers the source, the drain and the active layer. The second patterned transparent conductive layer is disposed on the insulating layer and includes a gate disposed above the active layer and a common electrode disposed above the pixel electrode. A fabrication method of a pixel structure is also provided.

Abstract: A non-volatile semiconductor memory device according to an embodiment includes a plurality of first wiring lines that extend in a first direction, a plurality of second wiring lines that extend in a second direction intersecting the first direction to cross the first wiring lines, and memory cells, each of which is provided at a portion where the first wiring line crosses the second wiring line. The memory cell includes a variable resistance layer in the space between the wiring lines where the first wiring line crosses the second wiring line, a seam in the variable resistance layer extending in a direction between the first wiring layer and the second wiring layer, and a metal supply layer that comes in contact with the variable resistance layer and the seam.

Abstract: A semiconductor image sensor device having a negatively-charged layer includes a semiconductor substrate having a p-type region, a plurality of radiation-sensing regions in the p-type region proximate a front side of the semiconductor substrate, and a negatively-charged layer adjoining the p-type region proximate the plurality of radiation-sensing regions. The negatively-charged layer may be an oxygen-rich silicon oxide, a high-k metal oxide, or a silicon nitride formed as a liner in a shallow trench isolation feature, a sidewall spacer or an offset spacer of a transistor gate, a salicide-block layer, a buffer layer under a salicide-block layer, a backside surface layer, or a combination of these.

Abstract: The present invention makes it possible to inhibit an MR ratio from decreasing by high-temperature heat treatment in a magnetoresistive effect element using a perpendicular magnetization film. The magnetoresistive effect element includes a data storage layer, a data reference layer, and an MgO film interposed between the data storage layer and the data reference layer. The data storage layer includes a CoFeB film coming into contact with the MgO film, a perpendicular magnetization film, and a Ta film interposed between the CoFeB film and the perpendicular magnetization film. The CoFeB film is magnetically coupled to the perpendicular magnetization film through the Ta film.

Abstract: Provided is a light emitting device having a phosphor layer on a surface of a semiconductor light emitting element and reducing unevenness in light distribution color, and a method of manufacturing the same. A light emitting device 100 includes a light emitting element 20 with a supporting body which is composed of a semiconductor light emitting element 1 and a supporting body 10, and a phosphor layer 7 which continuously covers an upper surface and side surfaces of the semiconductor light emitting element 1, and side surfaces of the supporting body 10. The phosphor layer 7 is configured such that at least a lower portion of the side surface of the supporting body 10 is thinner than the upper surface and the side surface of the semiconductor light emitting element 1.

Abstract: The device for charge carrier modulation is a current-controlled component, which has semiconductor layers arranged on top of each other. The organic semiconductor layers arranged on top of each other are an electron transport layer, which is arranged between a first and a second hole transport layer, and/or a hole transport layer, which is arranged between a first and a second electron transport layer. The respective central layer is the modulation layer having a contact for a modulation voltage. By applying a modulation voltage, a modulation current flow is generated over the modulation layer. The modulation current flow influences the component current flow which flows from the first into the second hole or electron transport layer via the respective modulation layer.

Abstract: Solid state lighting dies and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting die includes a substrate material, a first semiconductor material, a second semiconductor material, and an active region between the first and second semiconductor materials. The second semiconductor material has a surface facing away from the substrate material. The solid state lighting die also includes a plurality of openings extending from the surface of the second semiconductor material toward the substrate material.

Abstract: A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped-well that is disposed below and engulfing the U-shaped bend.

Abstract: Provided is an organic light-emitting display apparatus including a substrate; a first pixel electrode for first color emission, a second pixel electrode for second color emission, and a third pixel electrode for third color emission, the first pixel electrode, the second pixel electrode, and the third pixel electrode being spaced apart from each other on the substrate; a first color emission layer on the first pixel electrode, a second color emission layer on the second pixel electrode, and a third color emission layer on the third pixel electrode; an opposite electrode on the first color emission layer, the second color emission layer, and the third color emission layer; and a capping layer that includes a same material as the opposite electrode and is porous.

Abstract: A light emitting device package includes substrate; first and second conduction members on the substrate; a light emitting diode on the substrate, the light emitting diode being electrically connected with the first and second conduction members; and a phosphor layer on the light emitting diode.

Abstract: A liquid crystal display device includes a terminal in which a first insulating film and a second insulating film are formed on a terminal metal, a contact hole is formed on the first insulating film and the second insulating film, and a first ITO is formed on the contact hole and the second insulating film. The terminal is connected to a different circuit through an ACF including conductive particles. The contact hole includes a region in which a second ITO is stacked on the first insulating film and the first ITO is stacked on the second ITO in the contact hole. A width s of a portion where the terminal metal contacts the first ITO in the contact hole is s<d, where the diameter of the conductive particle is d.

Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

Abstract: A MEMS device and a method to manufacture a MEMS device are disclosed. An embodiment includes forming trenches in a first main surface of a substrate, forming conductive fingers by forming a conductive material in the trenches and forming an opening from a second main surface of the substrate thereby exposing the conductive fingers, the second main surface opposite the first main surface.