Patents Examined by Scott R. Wilson
  • Patent number: 9659981
    Abstract: A semiconductor image sensor device having a negatively-charged layer includes a semiconductor substrate having a p-type region, a plurality of radiation-sensing regions in the p-type region proximate a front side of the semiconductor substrate, and a negatively-charged layer adjoining the p-type region proximate the plurality of radiation-sensing regions. The negatively-charged layer may be an oxygen-rich silicon oxide, a high-k metal oxide, or a silicon nitride formed as a liner in a shallow trench isolation feature, a sidewall spacer or an offset spacer of a transistor gate, a salicide-block layer, a buffer layer under a salicide-block layer, a backside surface layer, or a combination of these.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shyh-Fann Ting, Chih-Yu Lai, Cheng-Ta Wu, Yeur-Luen Tu, Ching-Chun Wang
  • Patent number: 9653677
    Abstract: The present invention makes it possible to inhibit an MR ratio from decreasing by high-temperature heat treatment in a magnetoresistive effect element using a perpendicular magnetization film. The magnetoresistive effect element includes a data storage layer, a data reference layer, and an MgO film interposed between the data storage layer and the data reference layer. The data storage layer includes a CoFeB film coming into contact with the MgO film, a perpendicular magnetization film, and a Ta film interposed between the CoFeB film and the perpendicular magnetization film. The CoFeB film is magnetically coupled to the perpendicular magnetization film through the Ta film.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: May 16, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Eiji Kariyada, Katsumi Suemitsu
  • Patent number: 9653659
    Abstract: Provided is a light emitting device having a phosphor layer on a surface of a semiconductor light emitting element and reducing unevenness in light distribution color, and a method of manufacturing the same. A light emitting device 100 includes a light emitting element 20 with a supporting body which is composed of a semiconductor light emitting element 1 and a supporting body 10, and a phosphor layer 7 which continuously covers an upper surface and side surfaces of the semiconductor light emitting element 1, and side surfaces of the supporting body 10. The phosphor layer 7 is configured such that at least a lower portion of the side surface of the supporting body 10 is thinner than the upper surface and the side surface of the semiconductor light emitting element 1.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: May 16, 2017
    Assignee: NICHIA CORPORATION
    Inventors: Takeshi Ikegami, Tadao Hayashi, Hiroto Tamaki
  • Patent number: 9627641
    Abstract: The device for charge carrier modulation is a current-controlled component, which has semiconductor layers arranged on top of each other. The organic semiconductor layers arranged on top of each other are an electron transport layer, which is arranged between a first and a second hole transport layer, and/or a hole transport layer, which is arranged between a first and a second electron transport layer. The respective central layer is the modulation layer having a contact for a modulation voltage. By applying a modulation voltage, a modulation current flow is generated over the modulation layer. The modulation current flow influences the component current flow which flows from the first into the second hole or electron transport layer via the respective modulation layer.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: April 18, 2017
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: G√ľnter Schmid, Dan Taroata
  • Patent number: 9620743
    Abstract: Provided is an organic light-emitting display apparatus including a substrate; a first pixel electrode for first color emission, a second pixel electrode for second color emission, and a third pixel electrode for third color emission, the first pixel electrode, the second pixel electrode, and the third pixel electrode being spaced apart from each other on the substrate; a first color emission layer on the first pixel electrode, a second color emission layer on the second pixel electrode, and a third color emission layer on the third pixel electrode; an opposite electrode on the first color emission layer, the second color emission layer, and the third color emission layer; and a capping layer that includes a same material as the opposite electrode and is porous.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: April 11, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kyul Han, Hyo-Yeon Kim, Hye-Yeon Shim, Sang-Woo Lee, Heun-Seung Lee, Sang-Woo Pyo
  • Patent number: 9620670
    Abstract: Solid state lighting dies and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting die includes a substrate material, a first semiconductor material, a second semiconductor material, and an active region between the first and second semiconductor materials. The second semiconductor material has a surface facing away from the substrate material. The solid state lighting die also includes a plurality of openings extending from the surface of the second semiconductor material toward the substrate material.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: April 11, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Casey Kurth, Thomas Gehrke, Kevin Tetz
  • Patent number: 9620498
    Abstract: A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped-well that is disposed below and engulfing the U-shaped bend.
    Type: Grant
    Filed: July 26, 2014
    Date of Patent: April 11, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Yi Su, Anup Bhalla, Daniel Ng
  • Patent number: 9614132
    Abstract: A light emitting device package includes substrate; first and second conduction members on the substrate; a light emitting diode on the substrate, the light emitting diode being electrically connected with the first and second conduction members; and a phosphor layer on the light emitting diode.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: April 4, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Yu Ho Won, Geun Ho Kim
  • Patent number: 9595641
    Abstract: A liquid crystal display device includes a terminal in which a first insulating film and a second insulating film are formed on a terminal metal, a contact hole is formed on the first insulating film and the second insulating film, and a first ITO is formed on the contact hole and the second insulating film. The terminal is connected to a different circuit through an ACF including conductive particles. The contact hole includes a region in which a second ITO is stacked on the first insulating film and the first ITO is stacked on the second ITO in the contact hole. A width s of a portion where the terminal metal contacts the first ITO in the contact hole is s<d, where the diameter of the conductive particle is d.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: March 14, 2017
    Assignee: Japan Display Inc.
    Inventor: Takahiro Nagami
  • Patent number: 9496233
    Abstract: An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: November 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wei Lin, Sheng-Yu Wu, Yu-Jen Tseng, Tin-Hao Kuo, Chen-Shien Chen
  • Patent number: 9487386
    Abstract: A MEMS device and a method to manufacture a MEMS device are disclosed. An embodiment includes forming trenches in a first main surface of a substrate, forming conductive fingers by forming a conductive material in the trenches and forming an opening from a second main surface of the substrate thereby exposing the conductive fingers, the second main surface opposite the first main surface.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: November 8, 2016
    Assignee: Infineon Technologies AG
    Inventor: Alfons Dehe
  • Patent number: 9466559
    Abstract: In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: October 11, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiromi Shigihara, Hiroshi Tsukamoto, Akira Yajima
  • Patent number: 9466815
    Abstract: An organic light emitting diode display includes a display substrate including a first substrate and a plurality of pixel light emitting units on the first substrate, and an encapsulation substrate including a second substrate facing the display substrate, and a main reflecting member on the second substrate, the main reflecting member including a light emitting opening at a position corresponding to at least one of the pixel light emitting units, and an auxiliary opening dividing the main reflecting member into a plurality of sub-reflecting members.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: October 11, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jin Koo Chung, Kyung Ho Kim, Sang Hoon Yim
  • Patent number: 9449927
    Abstract: A seal ring structure of an integrated circuit includes a seal ring and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes a top electrode, a bottom electrode disposed below the top electrode, and a first insulating layer disposed between the top electrode and the bottom electrode. The MIM capacitor is disposed within the seal ring and the MIM capacitor is insulated from the seal ring.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Tung-Liang Shao, Ching-Jung Yang, Yu-Chia Lai, Hao-Yi Tsai, Tsung-Yuan Yu
  • Patent number: 9443834
    Abstract: Solid state lights (SSLs) including a back-to-back solid state emitters (SSEs) and associated methods are disclosed herein. In various embodiments, an SSL can include a carrier substrate having a first surface and a second surface different from the first surface. First and second through substrate interconnects (TSIs) can extend from the first surface of the carrier substrate to the second surface. The SSL can further include a first and a second SSE, each having a front side and a back side opposite the front side. The back side of the first SSE faces the first surface of the carrier substrate and the first SSE is electrically coupled to the first and second TSIs. The back side of the second SSE faces the second surface of the carrier substrate and the second SSE is electrically coupled to the first and second TSIs.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: September 13, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Cem Basceri, Casey Kurth, Kevin Tetz
  • Patent number: 9425246
    Abstract: An organic light emitting display device includes a substrate including a display area and a non-display area, a plurality of scan lines extended in a first direction on the substrate, a plurality of data lines extended in a second direction intersecting the first direction, a plurality of first switching elements in the display area, the plurality of first switching elements being connected to the scan lines and data lines, organic emission layers connected to the first switching elements, first dummy lines between corresponding adjacent ones of the plurality of scan lines, the first dummy lines extending in the first direction, second switching elements disposed in the non-display area, the second switching elements being adjacent to first ends of the first dummy lines, and second dummy lines extended in the second direction, the second dummy lines being adjacent to the second switching elements.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: August 23, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Tae Gon Kim, Sung Ho Cho, Yong Chul Kim, Ji Yong Park, Dong-Yoon So, Mi Jin Yoon
  • Patent number: 9406518
    Abstract: A device with improved device performance, and method of manufacturing the same, are disclosed. An exemplary device includes a group III-V compound semiconductor substrate that includes a surface having a (110) crystallographic orientation, and a gate stack disposed over the group III-V compound semiconductor substrate. The gate stack includes a high-k dielectric layer disposed on the surface having the (110) crystallographic orientation, and a gate electrode disposed over the high-k dielectric layer.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: August 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Ching Cheng, Chih-Hsin Ko, Hsingjen Wann
  • Patent number: 9379230
    Abstract: A semiconductor crystal substrate includes a substrate; and a protection layer formed by applying nitride on a surface of the substrate. The protection layer is in an amorphous state in a peripheral area at an outer peripheral part of the substrate, and the protection layer is crystallized in an internal area of the protection layer that is inside the peripheral area of the protection layer.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: June 28, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Shuichi Tomabechi
  • Patent number: 9364922
    Abstract: A visually seamless method of joining a first piece of metal and a second piece of metal is described. The first piece of metal is placed in contact with an edge of the second piece of metal. In some embodiments, the edge includes a sacrificial lip. The first piece of metal forming a junction area with the edge of the second piece of metal, applying a forging force to the first piece of metal, the forging force having an effect of creating an extremely tight fit up between the first and the second pieces of metal, welding the first and the second pieces to form an assembly and forming a cosmetically enhancing protective layer on the surface of the assembly, the protective layer obscuring any visible artifacts on the surface of the assembly, the obscured visible artifacts including any discoloration or discontinuity created by the laser welding.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: June 14, 2016
    Assignee: Apple Inc.
    Inventors: Carlo Catalano, Derrick Jue, Brian Miehm, Takahiro Oshima, Masashige Tatebe
  • Patent number: 9356133
    Abstract: A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: May 31, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Christopher Boguslaw Kocon, Hideaki Kawahara, Simon John Molloy, Satoshi Suzuki, John Manning Savidge Neilson