Patents Examined by Scott R. Wilson
  • Patent number: 9348185
    Abstract: A pixel structure and a manufacturing method of the pixel structure are provided. The pixel structure includes a substrate, a transistor, a planarizing layer, a plurality of contact windows, and a pixel electrode layer. The transistor is disposed on the substrate and includes a gate, a source, and a drain. The planarizing layer is disposed on the gate, the source, and a portion of the drain. The contact windows penetrate the planarizing layer and expose another portion of the drain. The pixel electrode layer is disposed on the planarizing layer, on the another portion of the drain, and in the contact windows and is electrically connected to the drain.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 24, 2016
    Assignee: E INK HOLDINGS INC.
    Inventors: Chien-Han Chen, Chih-Cheng Wang, Shih-Fang Chen
  • Patent number: 9337356
    Abstract: Disclosed are systems, devices and methods for providing electrostatic discharge (ESD) protection for integrated circuits. In some implementations, first and second conductors with ohmic contacts on an intrinsic semiconductor region can function similar to an x-i-y type diode, where each of x and y can be n-type or p-type. Such a diode can be configured to turn on under selected conditions such as an ESD event. Such a structure can be configured so as to provide an effective ESD protection while providing little or substantially nil effect on radio-frequency (RF) operating properties of a device.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: May 10, 2016
    Assignee: Skyworks Solutions, Inc.
    Inventors: Kim Rene Smith, Paul T. DiCarlo, Michael David Hill
  • Patent number: 9324907
    Abstract: A light emitting diode (LED) includes an active layer having one or more multilayer potential barriers and at least one well layer. Each multilayer potential barrier includes interlacing first and second InAlGaN thin layers. The first and second InAlGaN thin layers have compositions selected with respect to the well layer such that a polarization effect is substantially reduced.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: April 26, 2016
    Inventors: Meng-Hsin Yeh, Jyh-Chiarng Wu, Guojun Lu
  • Patent number: 9312507
    Abstract: By introducing new concepts into a structure of a conventional organic semiconductor element and without using a conventional ultra thin film, an organic semiconductor element is provided which is more reliable and has higher yield. Further, efficiency is improved particularly in a photoelectronic device using an organic semiconductor. Between an anode and a cathode, there is provided an organic structure including alternately laminated organic thin film layer (functional organic thin film layer) realizing various functions by making an SCLC flow, and a conductive thin film layer (ohmic conductive thin film layer) imbued with a dark conductivity by doping it with an acceptor and a donor, or by the like method.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: April 12, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuo Tsutsui, Hiroko Yamazaki, Satoshi Seo
  • Patent number: 9306167
    Abstract: A field-emission device is disclosed. The device comprises a solid state structure formed of a crystalline material and an amorphous material, wherein an outer surface of the solid state structure is substantially devoid of the amorphous material, and wherein a p-type conductivity of the crystalline material is higher at or near the outer surface than far from the outer surface.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: April 5, 2016
    Assignee: Technion Research & Development Foundation Limited
    Inventors: Rafael Kalish, Moshe Tordjman
  • Patent number: 9293641
    Abstract: Inverted optical device. In accordance with an embodiment of the present invention, a plurality of piggyback substrates are attached to a carrier wafer. The plurality of piggyback substrates are dissimilar in composition to the carrier wafer. The plurality of piggyback substrates are processed, while attached to the carrier wafer, to produce a plurality of integrated circuit devices. A flip wafer is attached to the plurality of light emitting diodes, away from the carrier wafer and the carrier wafer is removed. The plurality of light emitting diodes may be singulated to form individual light emitting diode devices.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: March 22, 2016
    Assignee: Invensas Corporation
    Inventors: Ilyas Mohammed, Masud Beroz, Liang Wang
  • Patent number: 9263457
    Abstract: Cross-coupling between a gate conductor and an active region of a semiconductor substrate is provided by forming a gate dielectric layer on the semiconductor substrate and lithographically patterning the gate dielectric layer to form opening therein over a portion of the active region at which electrical contact with the gate conductor is desired. After implanting electrical dopants, a gate conductor layer is deposited and patterned. A remaining portion of the gate conductor layer includes an integral conductor structure, which includes a first portion overlying a gate dielectric over an active region and a second portion contacting the semiconductor material of the same active region or a different active region. The gate dielectric layer can be deposited within gate cavities in planarization dielectric material layer in a replacement gate scheme, or can be deposited on planar surfaces of active regions and/or shallow trench isolation structures in a gate first processing scheme.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: February 16, 2016
    Inventors: Viraj Y. Sardesai, Robert C. Wong
  • Patent number: 9252242
    Abstract: Diodes and resistors for integrated circuits are provided. Deep trenches (DTs) are integrated into the diodes and resistors for the purposes of thermal conduction. The deep trenches facilitate conduction of heat from a semiconductor-on-insulator substrate to a bulk substrate. Semiconductor fins may be formed to align with the deep trenches.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: February 2, 2016
    Assignee: International Business Machines Corporation
    Inventors: Theodorus Eduardus Standaert, Kangguo Cheng, Junjun Li, Balasubramanian Pranatharthi Haran, Shom Ponoth, Tenko Yamashita
  • Patent number: 9231228
    Abstract: An anode for an organic light emitting device which introduces a metal oxide to improve flows of charges, and an organic light emitting device using the anode. The anode for the organic light emitting device has excellent charge injection characteristics, thereby improving power consumption of the organic light emitting device.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: January 5, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Won-Jong Kim, Joon-Gu Lee, Ji-Young Choung, Jin-Baek Choi, Yeon-Hwa Lee, Chang-Ho Lee, Il-Soo Oh, Hyung-Jun Song, Jin-Young Yun, Young-Woo Song, Jong-Hyuk Lee
  • Patent number: 9231121
    Abstract: A high voltage circuit layout structure has a P-type substrate; a first N-type tub, a second N-type tub, a third N-type tub, a first P-type tub with a first width and a second P-type tub with a second width formed on the P-type substrate; wherein the first P-type tub is formed between the first N-type tub and the second N-type tub; and the second P-type tub is formed between the second N-type tub and the third N-type tub.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: January 5, 2016
    Assignee: Monolithic Power Systems, Inc.
    Inventor: Joseph Urienza
  • Patent number: 9209173
    Abstract: A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a trench-gate vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with the output circuit.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: December 8, 2015
    Assignee: Intersil Americas LLC
    Inventor: Francois Hebert
  • Patent number: 9190560
    Abstract: A method of forming a vertical III-nitride based light emitting diode structure and a vertical III-nitride based light emitting diode structure can be provided. The method comprises forming a III-nitride based light emitting structure on a silicon-on-insulator (SOI) substrate; forming a metal-based electrode structure on the III-nitride based light emitting structure; and removing the SOI substrate by a layer transfer process such that the metal-based electrode structure functions as a metal-based substrate of the light emitting structure.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: November 17, 2015
    Assignee: Agency for Science Technology and Research
    Inventors: Tripathy Sudhiranjan, Lin Vivian Kaixin, Teo Siew Lang, Dolmanan Surani Bin
  • Patent number: 9166036
    Abstract: Super-junction MOSFETs by trench fill system requires void-free filling epitaxial growth. This may require alignment of plane orientations of trenches in a given direction. Particularly, when column layout at chip corner part is bilaterally asymmetrical with a diagonal line between chip corners, equipotential lines in a blocking state are curved at corner parts due to column asymmetry at chip corner. This tends to cause points where equipotential lines become dense, which may cause breakdown voltage reduction. In the present invention, in power type semiconductor active elements such as power MOSFETs, a ring-shaped field plate is disposed in chip peripheral regions around an active cell region, etc., assuming a nearly rectangular shape. The field plate has an ohmic-contact part in at least a part of the portion along the side of the rectangle. However, in the portion corresponding to the corner part of the rectangle, an ohmic-contact part is not disposed.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: October 20, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Tomohiro Tamaki
  • Patent number: 9142473
    Abstract: The disclosure relates to a stacked type power device module. May use the vertical conductive layer for coupling the stacked devices, the electrical transmission path may be shortened. Hence, current crowding or contact damages by employing the conductive vias or wire bonding may be alleviated.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: September 22, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Yin-Po Hung, Tao-Chih Chang
  • Patent number: 9136388
    Abstract: Provided is a structure of a transistor, which enables a so-called normally-off switching element, and a manufacturing method thereof. Provided is a structure of a semiconductor device which achieves high-speed response and high-speed operation by improving on characteristics of a transistor, and a manufacturing method thereof. Provided is a highly reliable semiconductor device. In the transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating layer, and a gate electrode layer are stacked in that order. As the semiconductor layer, an oxide semiconductor layer which contains at least four kinds of elements of indium, gallium, zinc, and oxygen, and has a composition ratio (atomic percentage) of indium as twice or more as a composition ratio of gallium and a composition ratio of zinc, is used.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: September 15, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Takahashi, Tatsuya Honda, Takehisa Hatano
  • Patent number: 9130043
    Abstract: An object is to provide a method for manufacturing a highly reliable semiconductor device which includes a thin film transistor using an oxide semiconductor and having stable electric characteristics. In manufacture of a semiconductor device in which an oxide semiconductor is used for a channel formation region, after an oxide semiconductor film is formed, a conductive film including a metal, a metal compound, or an alloy that can absorb or adsorb moisture, a hydroxy group, or hydrogen is formed to overlap with the oxide semiconductor film with an insulating film provided therebetween. Then, heat treatment is performed in the state where the conductive film is exposed; in such a manner, activation treatment for removing moisture, oxygen, hydrogen, or the like adsorbed onto a surface of or in the conductive film is performed.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: September 8, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kengo Akimoto
  • Patent number: 9123691
    Abstract: Disclosed herein is a thin film transistor. The thin film transistor is characterized in having a source interconnect layer and a drain interconnect layer. The source electrode and the drain electrode are respectively disposed above and in contact with the source interconnect layer and the drain interconnect layer. The semiconductor layer is in contact with both the source interconnect layer and the drain interconnect layer, but is not in contact with the source electrode and the drain electrode.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 1, 2015
    Assignee: E Ink Holdings Inc.
    Inventors: Henry Wang, Chia-Chun Yeh, Xue-Hung Tsai, Chih-Hsuan Wang, Ted-Hong Shinn
  • Patent number: 9082722
    Abstract: A method for forming a semiconductor structure having a transistor device with a control electrode for controlling a flow of carriers between a first electrode and a second electrode. A passivation layer is deposited over the first electrode, the second electrode and the control electrode. An etch stop layer is deposited on the passivation layer over the control electrode. A dielectric layer is formed over the etch stop layer. A window is etched through a selected region in the dielectric layer over the control electrode, to expose a portion of the etch stop layer disposed over the control electrode. A metal layer is formed on a portion of the etch stop layer and the dielectric layer is also formed on the metal layer. A second metal layer is deposited on the portion of the dielectric layer formed on the first mentioned metal layer.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: July 14, 2015
    Inventors: Adrian D. Williams, Paul M. Alcorn
  • Patent number: 9076902
    Abstract: An integrated optical receiver architecture may be used to couple light between a multi-mode fiber (MMF) and silicon chip which includes integration of a silicon de-multiplexer and a high-speed Ge photo-detector. The proposed architecture may be used for both parallel and wavelength division multiplexing (WDM) based optical links with a data rate of 25 Gb/s and beyond.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: July 7, 2015
    Assignee: Intel Corporation
    Inventor: Ansheng Liu
  • Patent number: 9048203
    Abstract: A light emitting device having high definition, a high aperture ratio, and high reliability is provided. The present invention achieves high definition and a high aperture ratio with a full color flat panel display using red, green, and blue color emission light by intentionally forming laminate portions, wherein portions of different organic compound layers of adjacent light emitting elements overlap with each other, without depending upon the method of forming the organic compound layers or the film formation precision.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: June 2, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshiji Hamatani, Toru Takayama