Patents Examined by Scott R. Wilson
  • Patent number: 10020269
    Abstract: Disclosed are systems, devices and methods for providing electrostatic discharge (ESD) protection for integrated circuits. In some implementations, first and second conductors with ohmic contacts on an intrinsic semiconductor region can function similar to an x-i-y type diode, where each of x and y can be n-type or p-type. Such a diode can be configured to turn on under selected conditions such as an ESD event. Such a structure can be configured so as to provide an effective ESD protection while providing little or substantially nil effect on radio-frequency (RF) operating properties of a device.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: July 10, 2018
    Assignee: Skyworks Solutions. Inc.
    Inventors: Kim Rene Smith, Paul T. DiCarlo, Michael David Hill
  • Patent number: 10020444
    Abstract: According to one embodiment, a magnetic memory device includes an interlayer insulating film, a bottom electrode formed in the interlayer insulating film, a buffer layer formed on the bottom electrode, and a stacked structure formed on the buffer layer and including a first magnetic layer functioning as a magnetic storage layer, wherein a portion of the buffer layer located on a central portion of the bottom electrode is thicker than a portion of the buffer layer located on a peripheral portion of the bottom electrode.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: July 10, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shuichi Tsubata, Masatoshi Yoshikawa, Satoshi Seto
  • Patent number: 9947643
    Abstract: Inverted optical device. In accordance with an embodiment of the present invention, a plurality of piggyback substrates are attached to a carrier wafer. The plurality of piggyback substrates are dissimilar in composition to the carrier wafer. The plurality of piggyback substrates are processed, while attached to the carrier wafer, to produce a plurality of integrated circuit devices. A flip wafer is attached to the plurality of light emitting diodes, away from the carrier wafer and the carrier wafer is removed. The plurality of light emitting diodes may be singulated to form individual light emitting diode devices.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: April 17, 2018
    Assignee: INVENSAS CORPORATION
    Inventors: Ilyas Mohammed, Masud Beroz, Liang Wang
  • Patent number: 9947782
    Abstract: A semiconductor device has a semiconductor layer and a substrate. The semiconductor layer constitutes at least a part of a current path, and is made of silicon carbide. The substrate has a first surface supporting the semiconductor layer, and a second surface opposite to the first surface. Further, the substrate is made of silicon carbide having a 4H type single-crystal structure. Further, the substrate has a physical property in which a ratio of a peak strength in a wavelength of around 500 nm to a peak strength in a wavelength of around 390 nm is 0.1 or smaller in photoluminescence measurement. In this way, the semiconductor device is obtained to have a low on-resistance.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: April 17, 2018
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Harada, Makoto Sasaki, Taro Nishiguchi, Kyoko Okita, Keiji Wada, Tomihito Miyazaki
  • Patent number: 9929220
    Abstract: Thinned and highly reliable light emitting elements are provided. Further, light emitting devices in which light emitting elements are formed over flexible substrates are manufactured with high yield. One light emitting device includes a flexible substrate, a light emitting element formed over the flexible substrate, and a resin film covering the light emitting element, and in the light emitting element, an insulating layer serving as a partition has a convex portion and the convex portion is embedded in the resin film, that is, the resin film covers an entire surface of the insulating layer and an entire surface of the second electrode, whereby the light emitting element can be thinned and highly reliable. In addition, a light emitting device can be manufactured with high yield in a manufacturing process thereof.
    Type: Grant
    Filed: January 4, 2010
    Date of Patent: March 27, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Katayama, Shingo Eguchi, Yoshiaki Oikawa, Ami Nakamura, Satoshi Seo, Kaoru Hatano
  • Patent number: 9923101
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a floating substrate; and a capacitor grounded and connected to the floating substrate. A method of manufacturing a semiconductor structure is also provided.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: March 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiao-Tsung Yen, Yu-Ling Lin, Chin-Wei Kuo, Ho-Hsiang Chen, Chewn-Pu Jou, Min-Chie Jeng
  • Patent number: 9887317
    Abstract: A light-emitting device including a substrate; a first conductivity semiconductor layer disposed on the substrate; a first barrier disposed on the first conductivity semiconductor layer; a well disposed on the first barrier and including a first region having a first energy gap and a second region having a second energy gap and closer to the semiconductor layer than the first region; a second barrier disposed on the well; and a second conductivity semiconductor layer disposed on the second barrier; wherein the first energy gap decreases along a stacking direction of the light-emitting device and has a first gradient, the second energy gap increases along the stacking direction and has a second gradient, and an absolute value of the first gradient is smaller than an absolute value of the second gradient.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: February 6, 2018
    Assignee: EPISTAR CORPORATION
    Inventors: Tien-Chang Lu, Chiao-Yun Chang, Heng Li
  • Patent number: 9876012
    Abstract: A voltage converter includes an output circuit having a high-side device and a low-side device which can be formed on a single die (a “PowerDie”). The high-side device can include a lateral diffused metal oxide semiconductor (LDMOS) while the low-side device can include a trench-gate vertical diffused metal oxide semiconductor (VDMOS). The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with the output circuit.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: January 23, 2018
    Assignee: INTERSIL AMERICAS LLC
    Inventor: Francois Hebert
  • Patent number: 9842906
    Abstract: A MOSFET cell of a semiconductor device includes a polysilicon gate electrode and an n+-source region formed in an upper portion of an n?-drift layer. An interlayer insulating film covers the gate electrode. An Al source electrode extends on the interlayer insulating film. An Al gate pad is connected to the gate electrode. A barrier metal layer that prevents diffusion of aluminum is interposed between the source electrode and the interlayer insulating film, and between the gate pad and the gate electrode.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: December 12, 2017
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Eisuke Suekawa, Yasunori Oritsuki, Yoichiro Tarui
  • Patent number: 9831348
    Abstract: A thin film transistor is provided, and includes a gate electrode, a first gate dielectric layer, a second gate dielectric layer, a channel layer, a source electrode and a drain electrode. The gate electrode is disposed on a substrate. The first gate dielectric layer is disposed on the gate electrode and the substrate, and has a radio of the number of silicon-hydrogen bonds to the number of nitrogen-hydrogen bonds, in which the ratio is between 0.2 and 1.0. The second gate dielectric layer is disposed on the first gate dielectric layer, and has a radio of the number of silicon-hydrogen bond to the number of nitrogen-hydrogen bonds, in which the ratio is between 0.01 and 0.2. The channel layer is disposed on the second gate dielectric layer. The source electrode and drain electrode are disposed on the channel layer and located at two opposite sides of the channel layer.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: November 28, 2017
    Assignees: HannStar Display (Nanjing) Corporation, HannStar Display Corporation
    Inventor: Yung-Ching Wang
  • Patent number: 9825163
    Abstract: Super-junction MOSFETs by trench fill system requires void-free filling epitaxial growth. This may require alignment of plane orientations of trenches in a given direction. Particularly, when column layout at chip corner part is bilaterally asymmetrical with a diagonal line between chip corners, equipotential lines in a blocking state are curved at corner parts due to column asymmetry at chip corner. This tends to cause points where equipotential lines become dense, which may cause breakdown voltage reduction. In the present invention, in power type semiconductor active elements such as power MOSFETs, a ring-shaped field plate is disposed in chip peripheral regions around an active cell region, etc., assuming a nearly rectangular shape. The field plate has an ohmic-contact part in at least a part of the portion along the side of the rectangle. However, in the portion corresponding to the corner part of the rectangle, an ohmic-contact part is not disposed.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: November 21, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tomohiro Tamaki
  • Patent number: 9806201
    Abstract: A method for forming an oxide that can be used as a semiconductor of a transistor or the like is provided. In particular, a method for forming an oxide with fewer defects such as grain boundaries is provided. One embodiment of the present invention is a semiconductor device including an oxide semiconductor, an insulator, and a conductor. The oxide semiconductor includes a region overlapping with the conductor with the insulator therebetween. The oxide semiconductor includes a crystal grain with an equivalent circle diameter of 1 nm or more and a crystal grain with an equivalent circle diameter less than 1 nm.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: October 31, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshinori Yamada, Yusuke Nonaka, Masashi Oota, Yoichi Kurosawa, Noritaka Ishihara, Takashi Hamada, Mitsuhiro Ichijo, Yuji Egi
  • Patent number: 9799844
    Abstract: An organic light emitting element is disclosed which includes: an anode and a cathode formed on a substrate and disposed to face each other; and a stack formed between the anode and the cathode and configured to include a hole transport layer, a first light emission layer, a second emission layer and an electron transport layer. The first light emission layer adjacent to the anode includes a host with band gaps of 1.00 eV˜2.70 eV and 2.76 eV˜4.00 eV. Such an organic light emitting element allows at least two light emission layers to be included into a single stack so that a driving voltage is reduced.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: October 24, 2017
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Jae Il Song, Jeong Haeng Heo
  • Patent number: 9780335
    Abstract: Lamination transfer films and methods for transferring a structured layer to a receptor substrate. The transfer films include a carrier substrate having a releasable surface, a sacrificial template layer applied to the releasable surface of the carrier substrate and having a non-planar structured surface, and a thermally stable backfill layer applied to the non-planar structured surface of the sacrificial template layer. The sacrificial template layer is capable of being removed from the backfill layer, such as via pyrolysis, while leaving the structured surface of the backfill layer substantially intact.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: October 3, 2017
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Martin B. Wolk, Mieczyslaw H. Mazurek, Sergey Lamansky, Margaret M. Vogel-Martin, Vivian W. Jones, Olester Benson, Jr., Michael Benton Free, Evan L. Schwartz, Randy S. Bay, Graham M. Clarke
  • Patent number: 9741726
    Abstract: A memory device includes a capacitor, a tunneling-enhanced device, and a transistor. In accordance with an embodiment, capacitor has first and second electrodes wherein the first electrode of the capacitor serves as a control gate of the memory device. The tunneling-enhanced device has a first electrode and a second electrode, wherein the first electrode of the second capacitor serves as an erase gate of the memory device and the second electrode of the tunneling-enhanced device is coupled to the second electrode of the capacitor to form a floating gate. The transistor has a control electrode and a pair of current carrying electrodes, wherein the control electrode of the transistor is directly coupled to the floating gate. In accordance with another embodiment, a method for manufacturing the memory device includes a method for manufacturing the memory device.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: August 22, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Thierry Coffi Herve Yao, Gregory James Scott
  • Patent number: 9698273
    Abstract: A thin film transistor includes: a gate electrode and a pair of source-drain electrodes provided on a substrate; an oxide semiconductor layer provided between the gate electrode and the pair of source-drain electrodes, the oxide semiconductor layer forming a channel; a protection film provided over whole of a surface above the substrate; and a gate insulating film provided on a gate electrode side of the oxide semiconductor layer, the gate insulating film having end faces part or all of which are covered with the pair of source-drain electrodes or with the protection film.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: July 4, 2017
    Assignee: Joled Inc.
    Inventor: Tomoatsu Kinoshita
  • Patent number: 9685607
    Abstract: A non-volatile semiconductor memory device according to an embodiment includes a plurality of first wiring lines that extend in a first direction, a plurality of second wiring lines that extend in a second direction intersecting the first direction to cross the first wiring lines, and memory cells, each of which is provided at a portion where the first wiring line crosses the second wiring line. The memory cell includes a variable resistance layer in the space between the wiring lines where the first wiring line crosses the second wiring line, a seam in the variable resistance layer extending in a direction between the first wiring layer and the second wiring layer, and a metal supply layer that comes in contact with the variable resistance layer and the seam.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: June 20, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoshio Ozawa
  • Patent number: 9684216
    Abstract: A pixel structure includes a first patterned transparent conductive layer, an active layer, an insulating layer and a second patterned transparent conductive layer. The first patterned transparent conductive layer is disposed on a substrate and includes a source, a drain and a pixel electrode connected to the drain. The active layer connects the source and the drain. The insulating layer covers the source, the drain and the active layer. The second patterned transparent conductive layer is disposed on the insulating layer and includes a gate disposed above the active layer and a common electrode disposed above the pixel electrode. A fabrication method of a pixel structure is also provided.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: June 20, 2017
    Assignee: E INK HOLDINGS INC.
    Inventors: Chien-Han Chen, Chih-Cheng Wang, Shih-Fang Chen
  • Patent number: 9659981
    Abstract: A semiconductor image sensor device having a negatively-charged layer includes a semiconductor substrate having a p-type region, a plurality of radiation-sensing regions in the p-type region proximate a front side of the semiconductor substrate, and a negatively-charged layer adjoining the p-type region proximate the plurality of radiation-sensing regions. The negatively-charged layer may be an oxygen-rich silicon oxide, a high-k metal oxide, or a silicon nitride formed as a liner in a shallow trench isolation feature, a sidewall spacer or an offset spacer of a transistor gate, a salicide-block layer, a buffer layer under a salicide-block layer, a backside surface layer, or a combination of these.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shyh-Fann Ting, Chih-Yu Lai, Cheng-Ta Wu, Yeur-Luen Tu, Ching-Chun Wang
  • Patent number: 9653677
    Abstract: The present invention makes it possible to inhibit an MR ratio from decreasing by high-temperature heat treatment in a magnetoresistive effect element using a perpendicular magnetization film. The magnetoresistive effect element includes a data storage layer, a data reference layer, and an MgO film interposed between the data storage layer and the data reference layer. The data storage layer includes a CoFeB film coming into contact with the MgO film, a perpendicular magnetization film, and a Ta film interposed between the CoFeB film and the perpendicular magnetization film. The CoFeB film is magnetically coupled to the perpendicular magnetization film through the Ta film.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: May 16, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Eiji Kariyada, Katsumi Suemitsu