Abstract: A semiconductor device includes a semiconductor substrate and a first trench extending into or through the semiconductor substrate from a first side. The first trench is at least partially filled with a conductive material and electrically connected to the semiconductor substrate via a doped semiconductor layer at a sidewall of the first trench. A semiconductor layer adjoins the semiconductor substrate at the first side, and caps the first trench at the first side. A contact is disposed at a second side of the semiconductor substrate opposite to the first side. A method of manufacturing the semiconductor device is also provided.

Abstract: A method of removing a dummy gate dielectric layer is provided. Firstly a first plasma containing F is utilized to remove the dummy dielectric layer which contains Si and O. Then a second plasma containing H2 is utilized to remove fluorine compound on the surface of the semiconductor substrate. Since the fluorine residue formed after the first plasma treatment reacts with the second plasma to form a gaseous product HF, the fluorine element can be taken away from the semiconductor device with the HF, which prevents inversion layer offset and gate current leakage occurred in the subsequent processing steps due to the fluorine element.

Abstract: A method of an interfacial oxide layer formation comprises a plurality of steps. The step (S1) is to remove a native oxide layer from a surface of a substrate; the step (S2) is to form an oxide layer on a surface of a substrate by piranha solution (SPM); the step (S3) is to cleaning a surface of the oxide layer by standard clean 1 (SC1), and the step (S4) is to etch he oxide layer by a solution comprising diluted hydrogen fluoride (dHF) and ozonized pure water (DIO3).

Abstract: A method of planarizing a polysilicon gate are provided, comprising: growing a polysilicon gate layer on a substrate with trenches; depositing an oxide layer on the polysilicon gate layer; oxidizing the top portion of the polysilicon gate layer from the flat surface of the oxide layer, so as to form a silicon oxide interlayer in the top portion of the polysilicon gate layer; the bottom of the silicon oxide interlayer is aligned with or lower than the low-lying areas of surface of the polysilicon gate layer; removing the oxide layer and the silicon oxide interlayer, so as to obtain a flat surface of the polysilicon gate layer and avoid a series of problems resulted from the uneven surface in the subsequent processes.

Abstract: A memory having an array of perpendicular spin-transfer torque (STT) magnetic random access memory (MRAM) cells, wherein each cell has a magnetic layer stack. A magnetic shield disposed between the cells and having a minimum height of at least the height of the magnetic layer stacks.

Abstract: A display device includes a pixel section that includes a plurality of pixels each of which has a display element and which are disposed in a two-dimensional manner, and a driving circuit section that drives the plurality of pixels in order to perform display, in which a first floor including the driving circuit section and a second floor including the pixel section are laminated.

Abstract: An organic light emitting display device includes a first substrate, a light emitting structure, a light transmitting member, and a second substrate. The first substrate includes a pixel region and a transparent region. The light emitting structure is positioned in the pixel region of the first substrate. The light transmitting member is positioned in the transparent region. The second substrate is disposed on the light emitting structure and the light transmitting member. The light is not refracted in interfaces between the light transmitting member and the first substrate and between the light transmitting member and the second substrate.

Abstract: A method is provided for fabricating a semiconductor testing structure. The method includes providing a substrate having a to-be-tested device structure formed on a surface of the substrate, a dielectric layer formed on the surface of the substrate and a surface of the to-be-tested structure, and conductive structures and an insulation layer electrically insulating the conductive structures formed on a first surface of the dielectric layer. The method also includes planarizing the conductive structures and the insulation layer to remove the conductive structures and the insulation layer until the first surface of the dielectric layer is exposed; and bonding the first surface of the dielectric layer with a dummy wafer by an adhesive layer. Further, the method includes removing the substrate to expose a second surface relative to the first surface of the dielectric layer of the dielectric layer and a surface of the to-be-tested device structure.

Abstract: A semiconductor image sensor includes a substrate having a first side and a second side that is opposite the first side. An interconnect structure is disposed over the first side of the substrate. A plurality of radiation-sensing regions is located in the substrate. The radiation-sensing regions are configured to sense radiation that enters the substrate from the second side. A buffer layer is disposed over the second side of the substrate. A plurality of elements is disposed over the buffer layer. The elements and the buffer layer have different material compositions. A plurality of light-blocking structures is disposed over the plurality of elements, respectively. The radiation-sensing regions are respectively aligned with a plurality of openings defined by the light-blocking structures, the elements, and the buffer layer.

Abstract: A micromechanical structure, comprising a substrate having a through hole; a residual portion of a sacrificial oxide layer peripheral to the hole; and a polysilicon layer overlying the hole, patterned to have a planar portion; a supporting portion connecting the planar portion to polysilicon on the residual portion; polysilicon stiffeners formed extending beneath the planar portion overlying the hole; and polysilicon ribs surrounding the supporting portion, attached near a periphery of the planar portion. The polysilicon ribs extend to a depth beyond the stiffeners, and extend laterally beyond an edge of the planar portion. The polysilicon ribs are released from the substrate during manufacturing after the planar region, and reduce stress on the supporting portion.

Abstract: A semiconductor device includes an opening, a metal nitride layer, a bilayer metal layer and a conductive bulk layer. The opening is disposed in a first dielectric layer. The metal nitride layer is disposed in the opening. The bilayer metal layer is disposed on the metal nitride layer in the opening, where the bilayer metal layer includes a first metal layer and a second metal layer which is disposed on the first metal layer and has a greater metal concentration than that of the first metal layer. The conductive bulk layer is filled in the opening.

Abstract: A semiconductor image sensor includes a substrate having a first side and a second side that is opposite the first side. An interconnect structure is disposed over the first side of the substrate. A plurality of radiation-sensing regions is located in the substrate. The radiation-sensing regions are configured to sense radiation that enters the substrate from the second side. A plurality of light-blocking structures is disposed over the second side of the substrate. A passivation layer is coated on top surfaces and sidewalls of each of the light-blocking structures. A plurality of spacers is disposed on portions of the passivation layer coated on the sidewalls of the light-blocking structures.

Abstract: Embodiments of the present disclosure are directed toward interconnect routing configurations and associated techniques. In one embodiment, an apparatus includes a substrate, a first routing layer disposed on the substrate and having a first plurality of traces, and a second routing layer disposed directly adjacent to the first routing layer and having a second plurality of traces, wherein a first trace of the first plurality of traces has a width that is greater than a width of a second trace of the second plurality of traces. Other embodiments may be described and/or claimed.

Abstract: A tungsten film forming method includes: supplying a tungsten chloride gas as a source material of tungsten and a reducing gas towards a substrate to be processed under a depressurized atmosphere to cause reaction between the tungsten chloride gas and the reducing gas while heating the substrate to be processed, such that a main tungsten film is directly formed on a surface of the substrate to be processed without forming an initial tungsten film for nucleus generation.

Abstract: Various low stress compact device packages are disclosed herein. An integrated device package can include a first integrated device die and a second integrated device die. An interposer can be disposed between the first integrated device die and the second integrated device die such that the first integrated device die is mounted to and electrically coupled to a first side of the interposer and the second integrated device die is mounted to and electrically coupled to a second side of the interposer. The first side can be opposite the second side. The interposer can comprise a hole through at least the second side of the interposer. A portion of the second integrated device die can extend into the hole.

Abstract: A method of manufacturing an electronic device comprises: providing a layer of semiconductor material comprising a first portion, a second portion, and a third portion, the third portion connecting the first portion to the second portion and providing a semiconductive channel for electrical current flow between the first and second portions; providing a gate terminal arranged with respect to said third portion such that a voltage may be applied to the gate terminal to control an electrical conductivity of said channel; and processing at least one of the first and second portions so as to have an electrical conductivity greater than an electrical conductivity of the channel when no voltage is applied to the gate terminal. In certain embodiments, the processing comprises exposing at least one of the first and second portions to electromagnetic radiation. The first and second portions may be laser annealed to increase their conductivities.

Abstract: A light-emitting device of an embodiment includes a light-emitting element emitting blue excitation light and a first phosphor excited by the blue excitation light and emitting fluorescence. A peak wavelength of the fluorescence is not shorter than 520 nm and shorter than 660 nm and the peak wavelength of the fluorescence shifting in the same direction when a peak wavelength of the blue excitation light shifts. The first phosphor is one of a yellow phosphor emitting yellow fluorescence, a green phosphor emitting green fluorescence, a yellow-green/yellow phosphor emitting yellow-green/yellow fluorescence and a red phosphor emitting red fluorescence.

Abstract: A method of manufacturing an organic EL element having a pair of electrodes and an organic functional layer disposed therebetween, the pair of electrodes consisting of an upper electrode and a lower electrode, comprising: forming the upper electrode on the organic functional layer by a magnetron sputtering method with a film-forming power density no less than 4.5 W/cm2 and no greater than 9.0 W/cm2.

Abstract: An image sensor includes a substrate with a unit pixel defined by a first separation pattern, a photoelectric conversion part in the substrate, a photocharge storage in the substrate, the photocharge storage being adjacent to the photoelectric conversion part, a second separation pattern between the photoelectric conversion part and the photocharge storage, a shielding part on a bottom surface of the substrate to cover the photocharge storage, the shielding part including a first protrusion extending into the substrate and toward the first separation pattern, and an extension extending from the first protrusion to cover the bottom surface of the substrate; and an anti-reflection layer between the shielding part and the substrate, the anti-reflection layer having an overhang structure between the first protrusion and the extension.

Abstract: A method for manufacturing semiconductor devices includes following steps. A substrate including a first gate structure and a second gate structure formed thereon is provided. The first gate structure and the second gate structure are complementary to each other. Next, a first mask layer covering the second gate structure is formed and followed by forming first recesses in the substrate at two respective sides of the first transistor. Then, forming the first recesses, a first epitaxial layer is formed in each first recess. After forming the first epitaxial layers, a local protecting cap is formed on the first epitaxial layers and followed by removing the first mask layer.