Abstract: A wafer processing method of processing a wafer with a plurality of devices disposed in areas demarcated by projected division lines and formed on a face side thereof includes a protective member placing step of placing a protective member for protecting the face side of the wafer on the face side of the wafer which is divided into individual device chips, a resin laying step of laying a die-bonding resin on the reverse sides of the individual device chips by applying a die-bonding liquid resin on the reverse side of the wafer and hardening the applied die-bonding liquid resin, and a separation step of separating the device chips with the die-bonding liquid resin laid on the reverse sides thereof from the wafer.

Abstract: The present disclosure provides a method of making an integrated circuit. The method includes forming a gate stack on a semiconductor substrate; forming a stressed contact etch stop layer (CESL) on the gate stack and on the semiconductor substrate; forming a first dielectric material layer on the stressed CESL using a high aspect ratio process (HARP) at a deposition temperature greater than about 440 C to drive out hydroxide (OH) group; forming a second dielectric material layer on the first dielectric material layer; etching to form contact holes in the first and second dielectric material layers; filling the contact holes with a conductive material; and performing a chemical mechanical polishing (CMP) process.

Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. The method includes forming a main pattern on a substrate; forming a spacer on sidewalls of the main pattern; forming a cut pattern having an opening by a first lithography process; and performing a cut process to selectively remove portions of the spacer within the opening of the cut pattern while the main pattern remains unetched, thereby defining a circuit pattern by the main pattern and the spacer. The circuit pattern includes a sharp jog.

Abstract: A method of forming a metallization layer by ASAP is provided. Embodiments include forming an ULK layer; forming a SAC SiN layer over the ULK layer; forming mandrels directly on the SAC SiN layer; cutting the mandrels; selectively etching the SAC SiN layer across the cut mandrels, forming first trenches; filling the first trenches with a metal oxide; forming a conformal metal oxide layer over the cut mandrels, the metal oxide, and the SAC SiN layer; removing horizontal portions of the conformal metal oxide layer over the cut mandrels and the SAC SiN layer; removing the cut mandrels; removing exposed portions of the SAC SiN layer and etching the underlying ULK layer, forming second trenches; and stripping a remainder of the metal oxide, conformal metal oxide layer, and SAC SiN layer.

Abstract: Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.

Abstract: A method for processing a semiconductor wafer is provided. The method includes performing a discharging process over the semiconductor wafer in a discharging chamber which is enclosed. The method further includes processing the semiconductor wafer by use of a first processing module after the discharging process. During the discharging process, charged particles applied on the semiconductor wafer are tuned based on the characteristics of the surface of the semiconductor wafer.

Abstract: A display panel that includes a plurality of pixels, each pixel includes a first area including a display device; a second area including a first reflective member to reflect light received from the display device to an outside of the display panel for viewing, and a third area including a second reflective member reflecting external light to provide a mirror function when the display device is not displaying an image. The display device includes a pair of reflective electrodes to cause the light produced by the display device to propagate towards the second area. One of the two electrodes may further include a transparent conductive material to provide a waveguide function to the display device in the first area to improve coupling efficiency of the display panel.

Abstract: A quantum well infrared photodetector (QWIP) and method of making is disclosed. The QWIP includes a plurality of epi-layers formed into multiple periods of quantum wells, each of the quantum wells being separated by a barrier, the quantum wells and barriers being formed of II-VI semiconductor materials. A multiple wavelength QWIP is also disclosed and includes a plurality of QWIPs stacked onto a single epitaxial structure, in which the different QWIPs are designed to respond at different wavelengths. A dual wavelength QWIP is also disclosed and includes two QWIPs stacked onto a single epitaxial structure, in which one QWIP is designed to respond at 10 ?m and the other at 3-5 ?m wavelengths.

Abstract: Embodiments of the disclosure disclose an electroluminescence display device and a fabrication method thereof. The device comprises a color filter substrate. The color filter substrate comprises: a first substrate, and a first electrode, an organic electroluminescence layer and a second electrode sequentially provided on the first substrate. The color filter substrate further comprises: a first protective layer, provided on the second electrode and covering the second electrode and the organic electroluminescence layer below the second electrode; and a first connection electrode, provided on the first protective layer and connected to the second electrode.

Abstract: An integration method of fabricating optical sensor device and thin film transistor device includes the follow steps. A substrate is provided, and a gate electrode and a bottom electrode are formed on the substrate. A first insulating layer is formed on the gate electrode and the bottom electrode, and the first insulating layer at least partially exposes the bottom electrode. An optical sensing pattern is formed on the bottom electrode. A patterned transparent semiconductor layer is formed on the first insulating layer, wherein the patterned transparent semiconductor layer includes a first transparent semiconductor pattern covering the gate electrode, and a second transparent semiconductor pattern covering the optical sensing pattern. A source electrode and a drain electrode are formed on the first transparent semiconductor pattern.

Abstract: Embodiments described herein relate to a dual-band photodetector. The dual-band photodetector includes a barrier layer (10) disposed between two infrared absorption layers (8, 12) wherein the barrier layer (10) is lattice matched to at least one of the infrared absorption layers (8, 12). Furthermore, one infrared absorption layer includes dilute nitride to adjust the band gap to a desired cut-off wavelength while maintaining valence-band alignment with the barrier layer. Embodiments also relate to a system and processes for producing the photodetector fabricated from semiconductor materials.

Abstract: Disclosed herein is 3D memory with vertical NAND strings having a III-V compound channel, as well as methods of fabrication. The III-V compound has at least one group III element and at least one group V element. The III-V compound provides for high electron mobility transistor cells. Note that III-V materials may have a much higher electron mobility compared to silicon. Thus, much higher cell current and overall cell performance can be achieved. Also, the memory device may have better read-write efficiency due to much higher carrier mobility and velocity. The tunnel dielectric of the memory cells may have an Al2O3 film in direct contact with the III-V NAND channel. The drain end of the NAND channel may be a metal-III-V alloy in direct contact with a metal region. The body of the source side select transistor could be formed from the III-V compound or from crystalline silicon.

Abstract: A simplified manufacturing process stably produces a semiconductor device with high electrical characteristics, wherein platinum acts as an acceptor. Plasma treatment damages the surface of an oxide film formed on a n? type drift layer deposited on an n+ type semiconductor substrate. The oxide film is patterned to have tapered ends. Two proton irradiations are carried out on the n? type drift layer with the oxide film as a mask to form a point defect region in the vicinity of the surface of the n? type drift layer. Silica paste containing 1% by weight platinum is applied to an exposed region of the n? type drift layer surface not covered with the oxide film. Heat treatment inverts the vicinity of the surface of the n? type drift layer to p-type by platinum atoms which are acceptors. A p-type inversion enhancement region forms a p-type anode region.

Abstract: In some embodiments of the present disclosure, a method for manufacturing a thin film resistor after completing a copper chemical mechanical polishing (CMP) process on a copper process module may include: depositing a dielectric barrier layer across at least two structures; depositing a second dielectric layer atop the dielectric barrier as a hard mask; patterning a trench using photo lithography; etching the trench through the hard mask and stopping in or on the dielectric barrier; removing any remaining photoresist from the photo lithography process; etching the trench through the dielectric barrier thereby exposing a copper surface for each of the at least two copper structures; and depositing thin-film resistor material into the trench and bridging across the resulting at least two exposed copper surfaces.

Abstract: Methods of manufacture of integrated multi-layer magnetic films for use in passive devices in microelectronic applications. Soft ferromagnetic materials exhibiting high permeability and low coercivity are laminated together with insulating layers interposed. Electrical conductors coupled to interconnects are magnetically coupled to magnetic film layers to engender an inductor (self and mutual). Soft ferromagnetic materials are provided in an alternating array of parallel plate capacitors. Each alternating magnetic film is electrically coupled to either a primary or secondary electrical conductor interconnects and separated by an electrically insulating dielectric material. Alternatively, each alternating magnetic layer comprises an induced anisotropy material, which can also be combined with coiled conductor giving rise to a hybrid inductive/capacitive device. Also, soft ferromagnetic material are also selected and tuned to provide for FMR notch filtering.

Abstract: A method of manufacturing an insulated gate type switching device includes forming a gate trench that has a first portion with a first width in a first direction and a second portion with a second width in the first direction, the second width being wider than the first width. In an oblique implantation, second conductivity type impurities are irradiated at an irradiation angle inclined around an axis orthogonal to the first direction. The first width, the second width, and the irradiation angle are set such that the second conductivity type impurities are suppressed, at a first side surface of the first portion, from being implanted into a part below a lower end of a second semiconductor region, and at a second side surface of the second portion, the impurities are implanted into the part below the lower end of the second semiconductor region.

Abstract: Embodiments relate to photodetectors comprising: a substrate and a bulk-alloy infrared (IR) photo absorption layer disposed on the substrate to absorb photons in an infrared wavelength and having a graded section and an ungraded section. The photodetector comprises a unipolar barrier layer disposed on the bulk-alloy photo absorption layer. The graded section includes a graded alloy composition such that its energy bandgap is largest near the substrate and smallest near the unipolar barrier layer. The embodiments also relate to methods fabricating the photodetectors.

Abstract: Provided is a method for manufacturing a light emitting device that can manufacture the light emitting device at low cost. The manufacturing method of a light emitting device includes: a mounting step of mounting a plurality of light emitting elements at predetermined intervals in one direction on a substrate; a first resin formation step of continuously forming a first resin layer in the one direction to directly cover the light emitting elements mounted; a trench formation step of forming a trench between the light emitting elements in a direction intersecting the one direction; and a second resin charging step of charging a second resin into the trench.

Abstract: A semiconductor memory device includes a power decoupling capacitor (PDC) for preventing effective capacitance reduction during a high frequency operation. The semiconductor memory device includes the PDC to which a cell capacitor type decoupling capacitor is connected in series. The PDC includes a metal conductive layer electrically connected in parallel to a conductive layer formed on the same level as a bit line of a cell array region, wherein a plurality of decoupling capacitors in a first group and a plurality of decoupling capacitors in a second group are respectively connected to each other in parallel in a peripheral circuit region, and a storage electrode of the first group and a storage electrode of the second group are electrically connected to each other in series through the conductive layer.

Abstract: A method for making phase change memory cell includes following steps. A carbon nanotube wire is located on a surface of the substrate, wherein the carbon nanotube wire includes a first end and a second end opposite to the first end. A bending portion is formed by bending the carbon nanotube wire. A first electrode, a second electrode, and a third electrode are applied on the surface of the substrate, wherein the first electrode is electrically connected to the first end, the second electrode is electrically connected to the second end, and the third end is spaced from the bending portion of the carbon nanotube wire. A phase change layer is deposited to cover the bending structure and electrically connects to the third electrode.