Abstract: Provided are semiconductor devices and methods of manufacturing the same. The methods include providing a substrate including a first region and a second region, forming first mask patterns in the first region, and forming second mask patterns having an etch selectivity with respect to the first mask patterns in the second region. The first mask patterns and the second mask patterns are formed at the same time.

Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.

Abstract: Disclosed are a heat dissipation material comprising a metallic glass and an organic vehicle and a light emitting diode package including at least one of a junction part, wherein the junction part includes a heat dissipation material including a metallic glass.

Abstract: A method is presented for forming a Ge containing layer on a Si substrate. The method includes providing a crystalline Si substrate having a surface that has a crystallographic orientation, heating the Si substrate in a vacuum environment, exposing the Si substrate to a surfactant that is suitable for growth of the Ge containing layer on the crystalline Si using surfactant mediation, and thereafter growing the Ge containing layer on the surface of the heated Si substrate using a suitable sputtering technique. The conditions of the growth of the Ge containing layer are selected such that a thin Ge containing layer is formed on the surface of the Si substrate. The thin Ge containing layer has a surface that has crystallographic properties suitable for epitaxial growth of a layer of a further material on the surface of the thin Ge containing layer.

Abstract: A method for making phase change memory cell includes following steps. A carbon nanotube wire is located on a surface of the substrate, wherein the carbon nanotube wire includes a first end and a second end opposite to the first end. A bending portion is formed by bending the carbon nanotube wire. A first electrode, a second electrode, and a third electrode are applied on the surface of the substrate, wherein the first electrode is electrically connected to the first end, the second electrode is electrically connected to the second end, and the third end is spaced from the bending portion of the carbon nanotube wire. A phase change layer is deposited to cover the bending structure and electrically connects to the third electrode.

Abstract: A protective film material for protecting a surface of a wafer during a laser processing treatment contains a water soluble poly-N-vinyl acetamide. The protective film material is applied to the surface of the wafer which is then irradiated with a laser beam through the protective film material to perform a laser processing treatment. After the laser processing treatment, the protective film material is removed by washing with water.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a buffer layer on a substrate, an graded aluminum gallium nitride (AlGaN) layer disposed on the buffer layer, a gallium nitride (GaN) layer disposed on the graded AlGaN layer, a second AlGaN layer disposed on the GaN layer and a gate stack disposed on the second AlGaN layer. The gate stack includes one or more of a III-V compound p-doped layer, a III-V compound n-doped layer, an aluminum nitride (AlN) layer between the III-V compound p-doped and n-doped layers, and a metal layer formed over the p-doped, AlN, and n-doped layers. A dielectric layer can also underlie the metal layer.

Abstract: A semiconductor device includes an insulating layer on a semiconductor substrate, a bit line including TiAl and disposed on the insulating layer, a sidewall layer disposed on opposite sides of the bit line, a word line including TiN and disposed on the sidewall layer intersecting the bit line, and an air gap in an intersection region of the bit line and the word line. The thickness of the sidewall layer is larger than the thickness of the bit line. By having the TiAl bit line and TiN word line, the uniformity of the bit line and word line can be easily controlled to improve the performance of the semiconductor device.

Abstract: A light emitting device is provided with a growing base having specific geometry to prevent delamination between the encapsulant and the growing base, and thereby enhance structural reliability of the light emitting device. Furthermore, the light emitting efficiency as well as uniformity of light output of the light emitting device can be improved by forming the side surface of the growing base with at least a curved portion or slanted portion, and uneven structures can be formed on the curved portion or slanted portion to further improve the uniformity of light output. Furthermore, the light emitting diode chips can be fabricated by taking batch processing on the growing substrate, as provided in the wafer-level structure, with the advantages of saving cost, improving yield, etc.

Abstract: An object of the present invention is to provide an epitaxial wafer on which dislocation is preventable even when a LSA treatment is performed in device processes. An epitaxial wafer according to the present invention includes a wafer 11 whose nitrogen concentration is 1×1012 atoms/cm3 or more or whose specific resistance is 20 m?·cm or less by boron doping, and an epitaxial layer 12 provided on the wafer 11. On the wafer 11, if a thermal treatment is performed at 750° C. for 4 hours and then at 1,000° C. for 4 hours, polyhedron oxygen precipitates grow predominantly over plate-like oxygen precipitates. Therefore, in the device processes, plate-like oxygen precipitates cannot be easily formed. As a result, even when the LSA treatment is performed after various thermal histories in the device processes, it is possible to prevent the dislocation, which is triggered by oxygen precipitates, from generating.

Abstract: A method includes: forming a front surface structure of a semiconductor element on a front surface side of a semiconductor substrate; forming crystal defects in the semiconductor substrate by implanting charged particles into the semiconductor substrate; subjecting the semiconductor substrate to a heat treatment after having formed the crystal defects; attaching a supporting plate on the front surface side of the semiconductor substrate after the heat treatment; thinning the semiconductor substrate by grinding a back surface side of the semiconductor substrate to which the supporting plate has been attached; and forming a back surface structure of the semiconductor element on a back surface of the thinned semiconductor substrate.

Abstract: A fabricating method of a semiconductor device includes providing a substrate having a first region and a second region, forming a plurality of first gates in the first region of the substrate, such that the first gates are spaced apart from each other at a first pitch, forming a plurality of second gates in the second region of the substrate, such that the second gates are spaced apart from each other at a second pitch different from the first pitch, implanting an etch rate adjusting dopant into the second region to form implanted regions, while blocking the first region, forming a first trench by etching the first region between the plurality of first gates, and forming a second trench by etching the second region between the plurality of second gates.

Abstract: A display device related to one embodiment of the present invention includes a first substrate arranged with a plurality of pixels in the shape of a matrix, an insulation film arranged above the first substrate, a first electrode arranged above the insulation film, a second electrode arranged on an upper layer of the first electrode, and an organic EL layer arranged between the first electrode and the second electrode, wherein the insulation film includes a plurality of concave parts arranged corresponding to each of the plurality of pixels on the side of the first electrode, the first electrode, the organic EL layer and the second electrode are stacked in order above the insulation film and the concave part, and the an insulation layer is covering an end part of the first electrode arranged above the concave part is arranged on an interface part sectioning each of the plurality of pixels.

Abstract: A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first JTE region is set to 4.4×1017 cm?3 or higher and 6×1017 cm?3 or lower and an impurity concentration in a second JTE region is set to 2×1017 cm?3 or lower in a case of a Schottky diode, and an impurity concentration in the first JTE region is set to 6×1017 cm?3 or higher and 8×1017 cm?3 or lower and an impurity concentration in the second JTE region is set to 2×1017 cm?3 or lower in a case of a junction barrier Schottky diode.

Abstract: An organic light emitting display includes a first substrate comprising a major surface, and a pixel array formed over the major surface of the first substrate. The pixel array comprises a plurality of pixels formed over the first substrate and a plurality of spacers arranged over the first substrate. Each pixel comprises a first electrode and an organic emission layer formed over the first electrode. The pixel array provides a plurality of recesses and a plurality of bumps, and the plurality of recesses correspond to the first electrodes of the plurality of pixels and the plurality of bumps corresponds to the plurality of spacers.

Abstract: A technique of manufacturing a display device with high productivity is provided. In addition, a high-definition display device with high color purity is provided. By adjusting the optical path length between an electrode having a reflective property and a light-emitting layer by the central wavelength of a wavelength range of light passing through a color filter layer, the high-definition display device with high color purity is provided without performing selective deposition of light-emitting layers. In a light-emitting element, a plurality of light-emitting layers emitting light of different colors are stacked. The closer the light-emitting layer is to the electrode having a reflective property, the longer the wavelength of light emitted from the light-emitting layer is.

Abstract: The present invention provides a system comprising a semiconductor device, a method of controlling the semiconductor device in the system, and a method of manufacturing the semiconductor device in the system. The semiconductor device includes: a semiconductor region located in a semiconductor layer formed on an isolating layer; an ONO film on the semiconductor region; bit lines on either side of the semiconductor region, which are located in the semiconductor layer, and are in contact with the isolating layer; a device isolating region on two different sides of the semiconductor region from the sides on which the bit lines are located, the device isolating region being in contact with the isolating layer; and a first voltage applying unit that is coupled to the semiconductor region. In this semiconductor device, the semiconductor region is surrounded by the bit lines and the device isolating region, and is electrically isolated from other semiconductor regions.

Abstract: In a top-gate transistor in which an oxide semiconductor film, a gate insulating film, a gate electrode layer, and a silicon nitride film are stacked in this order and the oxide semiconductor film includes a channel formation region, nitrogen is added to regions of part of the oxide semiconductor film and the regions become low-resistance regions by forming a silicon nitride film over and in contact with the oxide semiconductor film. A source and drain electrode layers are in contact with the low-resistance regions. A region of the oxide semiconductor film, which does not contact the silicon nitride film (that is, a region overlapping with the gate insulating film and the gate electrode layer) becomes the channel formation region.

Abstract: An ESD device that includes a gate and an n-drain region isolated from the gate and formed at least partially within an n-well region, which in turn is formed at least partially within a deep n-well region. The doping levels of the n-drain region, the n-well region and the deep n-well region are in a descending order. The ESD device has trigger and holding voltages, above the operation voltage of its protected circuit, which are layout-configurable by altering the distance between the n-drain and a side edge of the n-well region.

Abstract: A rollable display device including a roll frame and a flexible display unit windable in the roll frame, the flexible display unit includes a flexible substrate, a display layer disposed on the flexible substrate, an encapsulation layer respectively disposed on and configured to seal the display layer, a polarization layer, a touch screen layer, and a protection layer sequentially disposed on the encapsulation layer, and adhesive layers disposed between the encapsulation layer and the polarization layer, the polarization layer and the touch screen layer, and the touch screen layer and the protection layer, in which each of the adhesive layers comprise first regions and second regions alternately disposed between a first end and a second end of the flexible display unit, and a modulus of the first regions is different from a modulus of the second regions.