Patents Examined by Selim Ahmed
  • Patent number: 9666667
    Abstract: Aspects of the present disclosure are directed toward apparatuses, methods, and systems that include at least two regions of a first semiconductor material and at least two regions of second semiconductor material that are alternatively interleaved. Additionally, the apparatuses, methods, and systems include a first electrode and a second electrode that can operate both as a source and drain. The apparatuses, methods, and systems also include a first gate electrode having multiple portions on the first semiconductor material and a second gate electrode having multiple portions on the second semiconductor material that bidirectionally control current flow between the first electrode and the second electrode.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: May 30, 2017
    Assignee: NXP B.V.
    Inventors: Peter Steeneken, Anco Heringa, Radu Surdeanu, Luc Van Dijk, Hendrik Johannes Bergveld
  • Patent number: 9660086
    Abstract: The present invention provides a fin-shaped field effect transistor (FinFET), comprises: a substrate having a fin structure; a plurality trenches formed on the fin structure with an alloy grown in the trenches; a gate structure on the fin structure perpendicular to an extending direction of the fin structure in-between the plurality of trenches; and an amorphous layer on a surface of the fin structure exposed by the gate structure and disposed in-between the gate structure and the alloy. The invention also provides a manufacturing method of a fin-shaped field effect transistor (FinFET).
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: May 23, 2017
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Chun-Yu Chen, Chung-Ting Huang, Ming-Hua Chang, Tien-Chen Chan, Yen-Hsing Chen, Hsin-Chang Wu
  • Patent number: 9653420
    Abstract: Microelectronic devices and methods for filling vias and forming conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece having a plurality of dies and at least one passage extending through the microfeature workpiece from a first side of the microfeature workpiece to an opposite second side of the microfeature workpiece. The method can further include forming a conductive plug in the passage adjacent to the first side of the microelectronic workpiece, and depositing conductive material in the passage to at least generally fill the passage from the conductive plug to the second side of the microelectronic workpiece.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: May 16, 2017
    Assignee: Micron Technology, Inc.
    Inventors: William M. Hiatt, Kyle K. Kirby
  • Patent number: 9647152
    Abstract: A sensor circuit includes a transistor comprising an oxide semiconductor; a first circuit which supplies one of a first potential and a second potential; a first switch; a second switch; and a second circuit to which a current flowing between a source and a drain of the transistor is applied via the second switch when the first potential is applied to a gate of the transistor. The first potential is lower than a potential of the source or a potential of the drain of the transistor, and the second potential is higher than the potential of the source or the potential of the drain of the transistor. The first switch electrically connects the source and the drain of the transistor when the second potential is applied to the gate of the transistor, and electrically isolates them when the first potential is applied to the gate of the transistor.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: May 9, 2017
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Jun Koyama, Tomokazu Yokoi, Tsutomu Murakawa
  • Patent number: 9647053
    Abstract: Integrated multi-layer magnetic films for use in passive devices in microelectronic applications and methods of manufacture thereof. Soft ferromagnetic materials exhibiting high permeability and low coercivity are laminated together with insulating layers interposed. Electrical conductors coupled to interconnects are magnetically coupled to magnetic film layers to engender an inductor (self and mutual). Soft ferromagnetic materials are provided in an alternating array of parallel plate capacitors. Each alternating magnetic film is electrically coupled to either a primary or secondary electrical conductor interconnects and separated by an electrically insulating dielectric material. Alternatively, each alternating magnetic layer comprises an induced anisotropy material, which can also be combined with coiled conductor giving rise to a hybrid inductive/capacitive device. Also, soft ferromagnetic material are also selected and tuned to provide for FMR notch filtering.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: May 9, 2017
    Assignee: Ferric Inc.
    Inventors: Noah Andrew Sturcken, Ryan Davies
  • Patent number: 9627201
    Abstract: In a method of forming holes, a plurality of guide patterns physically spaced apart from each other is formed on an object layer. The guide pattern has a ring shape and includes a first opening therein. A self-aligned layer is formed on the object layer and the guide patterns to fill the first opening. Preliminary holes are formed by removing portions of the self-aligned layer which are self-assembled in the first opening and between the guide patterns neighboring each other. The object layer is partially etched through the preliminary holes.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: April 18, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Woo Nam, Eun-Sung Kim
  • Patent number: 9627468
    Abstract: Provided is a capacitor structure including a substrate, a dielectric layer, a first conductive layer, and a cup-shaped capacitor. The dielectric layer is located on the substrate. The first conductive layer is located in the dielectric layer. The cup-shaped capacitor penetrates through the first conductive layer and is located in the dielectric layer. The cup-shaped capacitor includes a bottom electrode, a capacitor dielectric layer, and a top electrode. Two sidewalls of the bottom electrode are electrically connected to the first conductive layer. The capacitor dielectric layer covers a surface of the bottom electrode. The top electrode covers a surface of the capacitor dielectric layer. The capacitor dielectric layer is located between the top electrode and the bottom electrode. A top surface of the bottom electrode is lower than a top surface of the top electrode. Also the invention provides a method of manufacturing the capacitor structure.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: April 18, 2017
    Assignee: Powerchip Technology Corporation
    Inventors: Shyng-Yeuan Che, Hsin-Lan Hsueh
  • Patent number: 9614157
    Abstract: An organic light emitting diode (OLED) display includes an OLED display panel having a substrate; a plurality of scan lines formed on the substrate; a plurality of data lines crossing the plurality of scan lines; cover lines covering the data lines; a plurality of switching elements coupled to the plurality of scan lines and the plurality of data lines; and a plurality of organic light emitting diodes coupled to the plurality of switching elements; and upper and lower data drivers respectively located at upper and lower parts of the OLED display panel, wherein the data lines include an upper data line and a lower data line that are separated from each other, and the cover lines include upper and lower cover lines that are separated from each other.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: April 4, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong-Hyun Park, Chun Gi You
  • Patent number: 9613988
    Abstract: In view of the problem that a reduced thickness of an EL film causes a short circuit between an anode and a cathode and malfunction of a transistor, the invention provides a display device that has a light emitting element including an electrode and an electroluminescent layer, a wire electrically connected to the electrode of the light emitting element, a transistor provided with an active layer including a source, a drain and a channel forming region, and a power supply line electrically connected to one of the source and the drain of the transistor, wherein the wire is electrically connected to the other of the source and the drain of the transistor, and the width of a part of the electrode in the vicinity of a portion where the electrode is electrically connected to the wire is smaller than that of the electrode in the other portion.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: April 4, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 9608170
    Abstract: A method of manufacturing a semiconductor light emitting element includes providing a semiconductor stacked layer body; forming an insulating layer on a portion of the semiconductor stacked layer body; forming a light-transmissive electrode covering an upper surface of the semiconductor stacked layer body and an upper surface of the insulating layer, and on a region at least partially overlapping a region for disposing an extending portion in a plan view; forming a light reflecting layer in each of the openings of the light-transmissive electrode; forming a protective layer on a main surface side of the semiconductor stacked layer body; forming a mask on an upper surface of the protective layer except for the region for forming the pad electrode; etching the protective layer to form an opening in the protective layer; and forming a pad electrode in the opening of the protective layer.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: March 28, 2017
    Assignee: NICHIA CORPORATION
    Inventors: Shun Kitahama, Keiji Emura, Shinichi Daikoku
  • Patent number: 9601585
    Abstract: A transistor includes an isolation region surrounding an active region. The transistor also includes a gate dielectric layer over a portion of the active region. The transistor further includes a gate electrode over the gate dielectric layer. The portion of the active region under the gate dielectric layer includes a channel region between a drain region and a source region, and at least one wing region adjoining the channel region. The at least one wing region has a base edge adjoining the channel region. The at least one wing region is polygonal or curved.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: March 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Liang Chu, Fei-Yuh Chen, Yi-Sheng Chen, Shih-Kuang Hsiao, Chun Lin Tsai, Kong-Beng Thei
  • Patent number: 9601409
    Abstract: The present disclosure relates to a method of forming a back-end-of-the-line metal contact that eliminates RC opens caused by metal dishing during chemical mechanical polishing. The method is performed by depositing a sacrificial UV/thermal decomposition layer (UTDL) above an inter-level dielectric (ILD) layer. A metal contact is formed that extend through the ILD layer and the sacrificial UTDL. A chemical mechanical polishing (CMP) process is performed to generate a planar surface comprising the sacrificial UTDL. The sacrificial UTDL is then removed through an ultraviolet exposure or a thermal anneal, so that the metal contact protrudes from the ILD layer.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Hsien Lu, Chia-Fang Tsai
  • Patent number: 9601391
    Abstract: A method and system are provided for determining mechanical stress experienced by a film during fabrication thereof on a substrate positioned in a vacuum deposition chamber. The substrate's first surface is disposed to have the film deposited thereon and the substrate's opposing second surface is a specular reflective surface. A portion of the substrate is supported. An optical displacement sensor is positioned in the vacuum deposition chamber in a spaced-apart relationship with respect to a portion of the substrate's second surface. During film deposition on the substrate's first surface, displacement of the portion of the substrate's second surface is measured using the optical displacement sensor. The measured displacement is indicative of a radius of curvature of the substrate, and the radius of curvature is indicative of mechanical stress being experienced by the film.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: March 21, 2017
    Assignee: The United States of America as Represented by the Administrator of the National Aeronautics and Space Administration
    Inventor: David M. Broadway
  • Patent number: 9595585
    Abstract: A method of manufacturing a semiconductor device includes forming a PMOS region and an NMOS region in a semiconductor substrate, forming dummy gate structures in the PMOS and NMOS regions, and forming a gate hard mask layer overlying top portions and sidewalls of the dummy gate structures. The method includes forming silicon carbon regions embedded in the semiconductor substrate on both sides of the dummy gate structure in the NMOS region, removing the hard mask layer on top of the dummy gate in the NMOS region, and forming silicon germanium regions embedded in the semiconductor substrate on both sides of the dummy gate structure in the PMOS region. After forming the silicon carbon regions and the silicon germanium regions, while retaining the hard mask layer on top of the dummy gates in the PMOS region, performing ion implant to form source/drain regions in the NMOS region and the PMOS region.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: March 14, 2017
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Gang Mao
  • Patent number: 9589830
    Abstract: A method for transferring a useful layer onto a support includes the following processes: formation of a fragilization plane through the implantation of light species into a first substrate in such a way as to form a useful layer between this plane and a surface of the first substrate; application of the support onto the surface of the first substrate to form an assembly to be fractured having two exposed sides; thermal fragilization treatment of the assembly to be fractured; and initiation and self-sustained propagation of a fracture wave in the first substrate along the fragilization plane. At least one of the sides of the assembly to be fractured is in close contact, over a contact zone, with an absorbent element suitable for capturing and dissipating acoustic vibrations emitted during the initiation and/or propagation of the fracture wave.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: March 7, 2017
    Assignees: Soitec, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed, Damien Massy, Frederic Mazen, Francois Rieutord
  • Patent number: 9580623
    Abstract: The present invention provides a patterning process, which comprises step of forming a BPSG film on the under layer film by using a composition for forming a coating type BPSG film including a base polymer and an organic compound with a content of 25 parts by mass or more of the organic compound with respect to 100 parts by mass of the base polymer, the base polymer having a silicon containing unit, a boron containing unit and a phosphorus containing unit with a total content of the boron containing unit and the phosphorus containing unit being 10 mol % or more, the organic compound having two or more hydroxyl groups or carboxyl groups per one molecule.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: February 28, 2017
    Assignees: SHIN-ETSU CHEMICAL CO., LTD., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Seiichiro Tachibana, Yoshinori Taneda, Rie Kikuchi, Tsutomu Ogihara, Yoshio Kawai, Karen Petrillo, Martin Glodde
  • Patent number: 9583366
    Abstract: A method of feeding underfill material to fill a space between a semiconductor die and a substrate onto which the semiconductor die has been bonded, the method comprises positioning a stencil over the semiconductor die. The stencil has an elongated slot extending adjacent to an edge of the semiconductor die. Underfill material is printed through the slot such that the underfill material falls through the slot onto the substrate next to the edge of the semiconductor die. Thereafter, the underfill material is heated such that the underfill material flows across the space between the semiconductor die and the substrate from the edge of the semiconductor die to an opposite edge thereof through capillary action.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: February 28, 2017
    Assignee: ASM TECHNOLOGY SINGAPORE PTE LTD
    Inventors: Qinglong Zhang, John Hon Shing Lau, Ming Li, Michael Zahn, Yiu Ming Cheung
  • Patent number: 9577043
    Abstract: A semiconductor device includes a buffer layer on a semiconductor substrate including first and second regions, a first channel layer on the buffer layer of the first region, a second channel layer on the buffer layer of the second region, and a spacer layer between the second channel layer and the buffer layer. The buffer layer, the first and second channel layers, and the spacer layer are formed of semiconductor materials including germanium. A germanium concentration difference between the first and second channel layers is greater than a germanium concentration difference between the buffer layer and the second channel layer. The spacer layer has a germanium concentration gradient.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: February 21, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jongryeol Yoo, Hyun Jung Lee, Sunjung Kim, Seung Hun Lee, Eunhye Choi
  • Patent number: 9577223
    Abstract: Provided is an organic light emitting diodes (OLED) and method of manufacturing the OLED. The OLED includes: a substrate; a light scattering layer having an uneven shape on the substrate; a transparent electrode film provided directly on and in contact with the light scattering layer; an organic light emitting layer on the transparent electrode film; and an electrode on the organic light emitting layer. The method of manufacturing the OLED includes: disposing a light scattering layer on a substrate; providing a transparent electrode film on the light scattering layer; and transferring the transparent electrode film to be directly on and in contact with the light scattering layer.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: February 21, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jin Wook Shin, Jeong Ik Lee, HongKyw Choi, Jaehyun Moon, Jonghee Lee, Nam Sung Cho, Doo-Hee Cho, Chul Woong Joo, Jun-Han Han
  • Patent number: 9570476
    Abstract: The array substrate comprises: data lines and scanning lines in an insulating crossing arrangement, where the data lines comprise first data lines and second data lines, the first data lines are arranged in a same layer with the scanning lines; the second data lines electrically connecting the first data lines via first via holes; first signal lines and common electrodes arranged on a substrate, where the first signal lines are arranged insulating from and in a same layer with the second data lines, the first signal line comprises a main portion and a bending portion which is arranged adjacently to the second data line; and a second insulating layer arranged between the first signal lines and the common electrodes, where second via holes are arranged in the second insulating layer, and the common electrodes are electrically connected to the first signal lines via the second via holes.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: February 14, 2017
    Assignees: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD., TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventor: Hong Ding