Abstract: A method and apparatus for processing data using data compression. During compression, a relationship between a next data word and a previous data word is determined and that relationship is encoded into variable bit-length code words, the bit-length being inversely proportional to the probability of occurrence of the relationship between the data words. The encoded relationships are transmitted rather than the data words themselves. In one embodiment, a look-up table of code words is stored which is indexed according to the possible relationships. A relationship is determined between the previous and next data words and the relationship is matched to the index to find the corresponding code word in the look-up table. The corresponding code word is retrieved from the look-up table, is substituted for the relationship, and is transmitted.

Abstract: A digital-to-analog converter including a plurality of binarily-weighted stages each incorporating a differential switch-pair circuit which includes two matched bipolar switch transistors the bases of which are driven by a corresponding pair of complementary signal sources. Two additional switches are included in this circuit, with each such switch being connected between a respective signal source and its corresponding transistor control electrode. These two switches are both opened before the clock-controlled activation of the complementary signal sources. A short time after such activation, sufficient to assure that the complementary signal voltages have stabilized at their new values, the two additional switches are reclosed simultaneously by a single control signal so as to effect synchronized switchover of the two switch transistors at that instant.

Abstract: An appparatus for receiving signals from any of a plurality of sensor types is provided and includes pull-up circuitry connected to a circuit input; data edge conditioning circuitry having a digital output and an input connected to said circuit input; and an analog output connected to said circuit input and said pull-up circuitry.

Abstract: An interface circuit for use with process controllers permits analog signals to be input to a process controller through a binary interface of the process controller and permits analog signals to be output from the process controller through the binary interface. The input analog signal is converted to a digital sample of N bits. An identification pulse and the N bits of the digital sample are transmitted to the process controller at a rate selected for compatibility with the scan time of the process controller. The process controller includes a software routine for recognizing the identification pulse and the N bits of the digital sample. An equivalent approach is used for outputting analog signals through a binary interface of a process controller. The interface circuit can include multiple channels for inputting or outputting multiple analog signals.

Abstract: An analog-to-digital converter having at least one stage, each stage comprising an array of capacitors, one or more comparators, an operational amplifier, and switches. Each stage operates in two phases, the sampling phase and the amplifying phase. During the sampling phase, the input voltage is sampled on the capacitor array. During the amplifying phase, one plate of each capacitors is connected to the reference voltage, ground, or the output of the operational amplifier to produce a residue voltage. Each of the array is sequentially connected to the output of the operational amplifier as the input voltage increases. The resulting residue drop for each digital code increase is precisely equal to the full-scale voltage. Combined with over-range and digital error-correction, the resulting A/D converter exhibits excellent differential linearity.

Abstract: An apparatus and method are disclosed for converting an input data character stream into a variable length encoded data stream and encoding the variable length encoded date stream according to byte length. A 2 byte length is encoded by 2 bits having the values "00". Encoded lengths of 3 and 4 bytes are represented respectively by 2 bits having the values "01" and "10". Byte lengths of 5 to 7 are represented by 4 bits "1100" to "1110" and so on to thereby enable an efficient procedure for encoding the length of a bit string during compression.

Abstract: A sigma-delta technique is used to generate a digital representation of the incoming analog signal amplitude. The integration stage of the converter holds an analog error term relative to the ratio of an incoming analog input signal to a reference voltage. The incoming analog signal is disconnected at the end of the conversion. The error term is monitored through a comparator as charge packets are applied to the input of the integration stage. The number of charge packets needed to have the error term cross zero provides information which can be used to extend the resolution of the analog to digital converter.

Abstract: A "true" 16-bit second order Sigma-Delta based converter that has superior analog components and has a programmable comb filter which is coupled to the digital signal processor. This converter comprises a second order Sigma-Delta modulator and a programmable comb filter. The second order Sigma-Delta modulator dramatically attenuates the baseband quantization noise energy (which in turn increases the resolution of the converter), since its superior amplifiers and comparators enable it to oversample and coarsely quantize the analog input signal at a very high sampling frequency of 12 MHz. The amplifiers are class AB OTAs, which have cross coupled NMOS driven input stages, and cascoded output stages. Also, the common mode voltages are the optimal biasing points, and these voltages are kept constant by a differential input stage, by a PV independent temperature dependent current generator, by optimal device size, and by a common mode feedback circuitry.

Abstract: An improved multi-codebook phase-in coding process for coding electronic data wherein for each received electronic input data, the coding process detects whether that input data exceeds a current coding maximum, then selecting a codebook coding method from one or more codebook coding methods in response to detecting whether that input data exceeds the current coding maximum, and then encoding that input data in accordance to the selected codebook coding method to generate a coded output data. A corresponding codebook indicator is inserted into a generated coded output data stream to indicate which codebook method to use to decode the coded output data. During decoding, the decoding process detects for a decode method indicator associated with each encoded input data, and decodes in accordance to a decode method corresponding to the detected decode method indicator to generate a decoded output data.

Abstract: A coding system comprises the comparing circuit which compares a magnitude of the range on the number line which is allocated to the most probability symbol with a magnitude of the fixed range on the number line which is allocated to the Less Probability Symbol. If the range allocated to the MPS is smaller than that to the LPS, and when the symbol is the MPS, the range allocated to the LPS is generated. If the range allocated to the MPS is smaller than that to the LPS, and when the symbol is the LPS, the range allocated to the MPS is generated. By the system, a coding efficiency is improved especially when a probability of occurrence of LPS (Less Probability Symbol) is approximate to 1/2.

Abstract: A serial data decoder is described for decoding interleaved variable length and fixed length codes. The decoder includes a state machine which moves between a branching hierarchy of states in dependence upon the bits of received serial data. When the state machine reaches a state corresponding to a complete variable length code having been received, it then enters a delay state lasting for the length of time necessary to receive the following fixed length code prior to return to a reset state. The state machine can be implemented using a static ram 10 storing data including pointers for controlling the movements between states.

Abstract: An n-bit analog processing circuit constructed with network swappers has n stages and an input port for inputting an analog signal to be processed. Each of the n stages includes first and second reference input ports, at least one swappable network having first and second terminals, and a switching element that is responsive to a digital input signal for varying a connectivity of the first and second terminals with respect to the first and second reference input ports. Each of the n networks has a primary electrical characteristic that is binarily weighted with respect to others of the networks. The primary electrical characteristic may be resistance, capacitance, capacitive reactance, inductance, inductive reactance, voltage potential, gain, transconductance, superconductance, time delay, permeability, electrical or optical conductor length, and/or winding turns.

Abstract: An Operational Analog to Digital (SYMAD) Convertor cell for converting an analog signal into a discrete binary code. An analog signal is processed by sample and hold circuitry and then compared to a reference voltage by a comparator. The comparator output is the converted digital output. This output is coupled back to the control input of an analog switch which selects either the reference voltage or a predetermined potential, typically zero volts, to couple to an inverting input of an operational amplifier. The analog signal input is also coupled to the non-inverting input of the operational amplifier. The operational amplifier is configured as a differential amplifier with a gain of two. If the digital output of the comparator is a logic 1, then the operational amplifier output is two times the difference between the analog signal and the reference voltage. If the digital output of the comparator is a logic 0, then the output of the operational amplifier is two times the analog signal.

Abstract: A digital-to-analog converter (i.e., D/A converter) formed on a wafer comprises a decoder, transistors (e.g., field-effect transistors) and resistors. Since the wafer provides a gap between the p-well region and the n-well region, the resistance values of the resistors formed on the p-well region differ from those of the resistors formed on the n-well region. In order to cancel such difference between the resistance values, there are provided two series of resistors in parallel between a power-applying terminal and a ground terminal, wherein each of two series of resistors contain two kinds of resistors respectively formed on the p-well region and the n-well region, while a midpoint of the first series of resistors is connected with a midpoint of the second series of resistors. Due to the direct connection between two midpoints, the potential applied to these midpoints are stabilized and set at the certain fixed voltage.

Abstract: Base station equipment of a digital mobile communication system includes a digital audio signal processing apparatus provided for each message channel for low bit rate coding and decoding a digital audio signal. Each digital audio signal processing apparatus includes a plurality of memories that store a plurality of low bit rate coding/decoding programs differing from each other to comply with different low bit rate coding/decoding methods. A system control circuit determines the low bit rate coding/decoding method of an applied digital signal for controlling a selector to select a memory that stores the corresponding low bit rate coding/decoding program. As a result, the digital audio signal processing apparatus perform digital to digital conversion of the applied digital signal according to the low bit rate coding/decoding program stored in the selected memory.

Abstract: A sampling rate converter includes an arithmetic circuit for performing digital filtering processing for sampling rate conversion, and a circuit for calculating a sampling rate ratio. A memory circuit stores a plurality of groups of filter coefficients which are used in the digital filtering processing performed in the arithmetic circuit, corresponding to a plurality of sampling rate ratio ranges. A select circuit selects a filter coefficient group corresponding to the sampling rate ratio. The select circuit is arranged such that even if the sampling rate ratio is outside a sampling rate ratio range corresponding to a filter coefficient group selected at the present time, the select circuit continues to select the filter coefficient group selected at this time as long as the sampling rate ratio is within a predetermined range outside the sampling rate ratio range.

Abstract: A high-performance superconducting digital-to-analog (D/A) converter providing asynchronous high-speed, low-power D/A conversion. The high-performance superconducting D/A converter includes a double-junction superconducting quantum interference device (SQUID) voltage divider circuit, which generates a series of discrete binary voltages, and a double-junction SQUID voltage selector circuit, which selects the binary voltages in accordance with a digital input signal. The currents generated by the selected binary voltages are added together to produce an analog output current that represents the digital input.

Abstract: A plug-in timer has a set of input terminals and a set of output terminals as well as a contactor operable to make and/or break electrical connection between these sets of terminals in accordance with a pre-setable 24 hour program. The timer is powered from a small built-in battery, and comprises its own quartz clock and programming-and-control means. The contactor is actuated by a miniature DC motor through a gear and cam arrangement. The operation of the DC motor is controlled by the programming-and-control means, which provides power from the battery to the motor in accordance with a pre-set program; which pre-set program may be modified at any time by way of a keyboard and a numeric display means.The contactor operates by way of hard metal contacts and very little power dissipation occurs within the timer. The timer can be plugged into a special wall switch receptacle and then operates to programmably control the flow of power to the load controlled by this wall switch.

Abstract: Input values are data encoded for improved signal characteristics (e.g., limited maximum run length and limited cumulative DC-offset) so as to form "data codewords," and then a number of the data codewords, collectively referred to as a block, are error protection encoded, preferably using a conventional linear and systematic forward error control ("FEC") code, to yield an FEC code block. Preferably, an FEC code block is formed by generating a number of check bits or FEC bits equal to the number of data codewords in the block, and then concatenating one FEC bit and its binary complement with each data codeword, so that one FEC bit and its complement is interposed between each successive codeword.

Abstract: A method and apparatus for linearizing an analog signal. The signal is converted into a digital form and digital gain and offset words are fetched based upon the value of the measurement signal and any other parameters which affect linearity, such as temperature for example. The digital gain and offset words are converted to analog values and inserted into an analog signal path of the measurement signal.