Abstract: The circuit includes a filter to which an analog signal is applied, a quantizer driven by the filter, a sampler at a desired frequency driven by the quantizer and a PCM encoder driven by the sampler. The quantizer generates a quantize signal according to the received analog signal and further generates a difference signal according to the difference between a quantized signal and the analog signal. A feedback circuit feeds back the difference signal from the quantizer to a stage of the filter so that the overall transfer function from the input of the feedback circuit to the output of the filter is equivalent to a low pass filtering.

Abstract: An analog-to-digital converter (ADC) has at least one resistance ladder circuit for generating a stepped series of reference voltages and set of comparator circuits for comparing an input voltage, or a voltage derived therefrom, with at least a subset of the stepped series of reference voltages. The reference voltages from the resistance ladder circuit are stepped in 4 LSB increments, where 1 LSB is the voltage differential corresponding to a one bit change in the ADC output value. During an initial set of conversion cycles, a ten-bit digital conversion value representing the input voltage is generated. In a last conversion cycle, two additional bits of resolution are added to the conversion value using a "parallel successive approximation register" circuit. This last conversion cycle also corrects errors of up to .+-.6 LSB in the first ten bits of the digital conversion value.

Abstract: An apparatus and method of calibrating a digital to analog converter including means for establishing and storing a minimum and maximum analog endpoint value slightly in excess of the desired operating range of the DAC and then scaling each respective raw data point of the DAC within the established endpoint values.

Abstract: A digital/analog converter including four D/A conversion.The D/A convertor comprises four D/A conversion parts (DA1) to (DA4). On a single semiconductor chip the D/A convertion parts (DA1) to (DA4) are arranged so that the D/A conversion parts (DA1) and (DA3) are symmetric with respect to a first center line (L1), the first and fourth D/A conversion parts (DA1) and (DA4) are arranged symmetric with respect to a second center line (L2) which crosses the first center line (L1) at right angles and the second and third D/A conversion parts are arranged symmetric with respect to the second center line. Although the locations of the resistances of each of the conversion parts produces errors, these cancel each other out due to their arrangement.

Abstract: An encoding circuit converts successive bits of the original data to successive bits of coded data at a coding rate equal to m/n, where m and n are each an integer satisfying m<n, in accordance with a rule of a run-length-limited coding system and contains an encoder which inputs parallel m bits of the original data, and outputs parallel n bits of coded data corresponding to the input. Successive bits of data which are to be encoded are cyclically divided into a plurality of groups, and the data in the plurality of groups are input in a plurality of shift registers, respectively. Each of the plurality of shift registers simultaneously supplied a part of the m bits of the input to the encoder, synchronizing with a clock. The n bits of the output of the encoder is received in parallel in another shift register, and are serially output from the shift register, synchronizing with a second clock.

Abstract: There are provided 2.sup.n -number of data latches (2), 2.sup.n -number of dynamic range setting latches (7) and 2.sup.n -number of output dynamic range change circuits (8) in correspondence to 2.sup.n -number of D/A converters. Controlled by the outputs of AND gates (4), the respective dynamic range setting latches (7) output dynamic range setting data DR to the corresponding output dynamic range change circuits (8). The output dynamic range change circuits (8) change dynamic ranges for the analog outputs of the corresponding D/A converters (5) as a function of the dynamic range setting data DR to output the changed analog outputs from corresponding output terminals (26).This enables the dynamic ranges for the plurality of D/A converters to be set individually without the provision of further external terminals.

Abstract: An artificial network for encoding the binary on-state of one-out-of-N inputs, say j, when only one state is on at a time wherein the jth on-state is represented by a suitable output level of an N-input MP type neuron operating in the non-saturated region of the neuron output nonlinearity. A single line transmits the encoded amplitude level signal to a decoder having N single input neural networks.

Abstract: The method is founded on the GUAZZO algorithm and is adaptive as it does not require any prior statistical knowledge of source of message to be coded. The message is comprised of a sequence of symbols of the source which are represented by the indication of the direction "0" or "1" chosen at each node of a binary tree. According to the invention, the adaptiveness is obtained by associating with each node two finite-sized counters that count the "0"s and "1"s according to the routing of the tree. The contents of these counters enable the conditional probability of each of the elements "0" and "1" to be estimated at the node.

Abstract: A linear predictive ADC employs a fully feed forward design to extend its dynamic range, allow greater speed of operation, achieve stable operation and eliminate a requirement for sample-and-hold circuits. A first quantizer (Qc) converts an input analog signal to a digital format, while a signal predictor (32) predicts a subsequent value of the input signal. After conversion back to analog format, the predicted signal is compared with the actual subsequent value of the input signal to produce an error signal that is converted to a digital format by a second quantizer (Qf). The digital predicted signal is fed forward and combined with the digital error signal to produce a high precision digital output. The analog error signal is preferably amplified prior to digitation to take advantage of the full bit capacity of the second quanitzer (Qf), and then digitally de-amplified back to its original scale.

Abstract: An analog signal having a value A is converted into an n-bit digital signal. An optical calculation part performs a part of a calculation shown below for an A/D conversion as below.U.sub.i =[{{.SIGMA.(W.sub.ij .times.X.sub.j)+h.sub.i }.times.V}+A].times.Si . . . (1)The calculation of the equation (1) is performed fori=0, 1, . . . , n-1 respectively;the W.sub.ij is 0 if i.gtoreq.j.gtoreq.0, or -(2**j) if j>i.gtoreq.0; hi is -(2**i), or -{(2**i)-.epsilon.}(.vertline..epsilon..vertline..ltoreq.1);V and S.sub.i respectively have any desired positive values and the said .SIGMA. represents a summation of each expression following thereto for j=0, 1, . . . , n-1. The thresholding compares the result U.sub.i of the calculation of each equation (1) to a threshold value, and then 1 or 0 is selected. The result of the selection is then assigned to X.sub.i. The calculation of the equation (1) is then performed repeatedly until X.sub.i converge on solutions. The solution of each X.sub.

Abstract: A data compression/decompression method incorporating aliasing error reduction. An array of terrain data is first scanned for a set of modes and indexes are assigned to those modes. These modes are used as precision points for compression and decompression. A compressed index database is created using the associated modes for the original terrain data. If the number of modes exceed a predetermined number the number of modes is collapsed using an aliasing technique. The alias error is tracked during the compression cycle. Total aliasing error is kept to a local minimum. The compressed data is decompressed by decoding and accessing the index database for the elevation alias. Further compression is accomplished using a lossless coding technique.

Abstract: An A/D converter having a first divided reference voltage output circuit for dividing a first reference voltage by m and outputting a plurality of first divided reference voltages; a second divided reference voltage output circuit for dividing a second reference voltage by n and outputting a plurality of second divided reference voltages; a level shift circuit for level-shifting the plurality of second divided reference voltages in accordance with an input voltage to be A/D converted, and outputting a plurality of third divided reference voltages; a comparator circuit for comparing each of the plurality of first divided reference voltages with each of the plurality of third divided reference voltages, and outputting a combination of one of the first divided reference voltage and one of the third divided reference voltages having a smallest voltage difference therebetween; and an encoder circuit for outputting a digital signal converted from the input signal, in accordance with the combination outputted from t

Abstract: There is disclosed an ADC including a comparator which sets, bit-by-bit, a successive approximation binary register. Feedback means for auto-biasing, auto calibration, and offset compensation within the ADC are provided. The ADC sets itself to a high degree of accuracy automatically by reference to a master voltage reference. A number of identical ADCs are connected in parallel to provide an increased sampling rate. The ADC architecture compensates for component tolerance differences, for common mode noise, and for secondary parasitic effects. The ADC operates with high resolution at high speed (e.g., 10 bits at 50 MHz), and can be implemented in MOS technology with good integrated circuit chip yield and is compatible with new ASICs.

Abstract: The present invention provides a compact and robust architecture and a corresponding method to implement a monotonic algorithmic D/A converter that processes the bits of the digital input in the order from MSB to LSB, and a successive approximation A/D converter employing the intermediate conversion results of this D/A converter. The invention is aimed at applications requiring a dense integration in general VLSI technologies of multiple D/A and A/D converters, where individual trimming of components to compensate for component offsets and mismatches is virtually impossible. The architecture comprises four charge holding components, one switch for charge sharing, two bi-directional replication elements for charge storage and recall, and one comparator. Also described is an efficient way of performing pseudo-logarithmic compression of conversion values merely by adjusting the relative sizes of two of the charge holding components.

Abstract: The search position encoder includes a generally planar medium, a search probe and a device for moving the probe generally parallel to the surface of the planar medium, and indexing device for locating the actual position of the probe relative to a fixed location on the generally planar medium. A plurality of gratings consisting of alternating strips of conducting and non-conducting materials are arranged on or adjacent to the medium parallel to orthogonal axes of the medium, and a device for sensing the movement of the probe in a plane parallel to the gratings. The location of the probe may then be determined based upon the sensing of the passage of the probe relative to the gratings.

Abstract: A microprocessor (8) controlled power-saving electronic measuring system is disclosed. A load cell (1) generates an output signal indicative of the magnitude of the load applied to the cell (1). A DC power supply (2) is switched to supply the load cell (1) with power pulses (10) at varying frequencies and duty cycles determinable by the microprocessor (8) to optimize battery life. The microprocessor (8) determines the optimal duty cycle and frequency for the power pulses responsive to desired parameters. The circuitry of the present invention is located in close proximity to a temperature sensor (34) which accurately reads the temperatures of all of the components and compensates for all heat related inaccuracies simultaneously. The microprocessor (8) determines a temperature corrected value for the load cell (1) output via a previously programmed table containing the temperature response characteristics for the load cell (1) and the circuitry.

Abstract: A dual range A/D converter includes means for appending a predetermined number N of random noise bits to the N least significant bits of the digital signals output from one of the dual A/D converters, thereby providing a total output bit resolution that is independent of the input analog signal.

Abstract: This dielectric relaxation correction circuit for charge-redistribution A/D converters, which has a comparator 20 and operates in a sample, hold and conversion mode, comprises: a capacitor array 22, a replica capacitance 35, having a bottom plate, arranged so as to be subject to the same sequence of charging voltages that the array capacitors 22 experience but in a neutralizing manner such that an error in the capacitor array 22 voltage is neutralized by the same error in the replica capacitance 35, and; a sample and hold circuit (S/H) 36 for sampling an input signal voltage during the sample mode, wherein the sample and hold 36 is arranged to hold the bottom plate of the replica capacitance 35 at the input signal voltage. Other devices, systems and methods are also disclosed.

Abstract: A very high-speed, high-resolution, low-noise, subranging analog-to-digital (AJD) converter architecture is described. It employs several sample-and-hold circuits in parallel. Also, the second-stage fine quantization flash A/D converter circuit of the conventional subranging A/D converter is replaced with a hybrid subranging converter of higher resolution and linearity. This is shown to achieve a very high dynamic range by minimizing noise due to the sample-and-hold and fine quantization circuits. This architecture permits construction of 16 to 18 bit 10 MHz A/D converters applicable for airborne radar systems.

Abstract: An audio/video signal combination apparatus for a digital audio tape recorder, is capable of combining 10 bit audio signal with 5 bit video signal by an automatic addressing, comprising analog/digital converters for converting audio signal and video signal into 10 bit and 5 bit digital data, a frame memory for storing digitized video signal by one frame, a digital signal processor for processing the 10 bit audio data and the 5 bit video data to one byte recording signal, and an automatic addressing unit for inputting the 5 bit video data stored in the frame memory to the digital signal processor when the digital signal processor reads the 10 bit audio data.