Abstract: An information processing system includes a digital computing system, an analog processing device with an arrangement for converting electrical information to information of analog form, and an arrangement responsive to the analog information energy for producing output electrical information. Output data from the digital computing system is applied to the analog processing system via a D/A converter, and an A/D converter applies the output electrical information to the digital computing system. Data modified by the analog processing system may be employed to supplement data applied thereto in a random manner, or in a manner with a known transfer function, in order to introduce perturbations in the data to aid in subsequent processing thereof in the digital computing system.

Abstract: Comparators for use in a semi-flash analog-to-digital converter utilize switched capacitor inputs for effecting a subtraction of charge corresponding to the subtraction of voltages to obtain the most significant bit comparisons and least significant bit comparisons. In a preferred embodiment, a 6-input switched-capacitor comparator is employed in which an analog input signal, a most significant reference TAP, and the output from a digital-to-analog converter are sequentially coupled through a first capacitor to the input of an inverting amplifier. A second plurality of input terminals sequentially connects one-half the least significant bit reference potential, 0 volts, and a least significant reference voltage TAP through second capacitive means to the input of the inverting amplifier. One comparator can thereby perform both a most significant bit comparison and a least significant bit comparison in a semi-flash mode of operation.

Abstract: The present invention provides a digital to analog converter circuit comprising a digital to analog converter portion for accepting digital inputs indicative of a signal level and for producing an analog output indicative of a difference in signal level between one digital input and a previous digital input. An integrator is coupled to the digital to analog converter portion for integrating the analog output thereby producing a substantially smooth waveform. The digital to analog converter portion may comprise a plurality of current source type digital to analog converters having a common output terminal and the integrator may comprise an integrating capacitor. In such an embodiment the output from the common output terminal is indicative of a signal level difference determined by at least two of the digital inputs.

Abstract: An improved serial-parallel type A/D converter is disclosed herein. A gate circuit 7 applies signals S11' to S14' provided from an encoder 3 only in a fine comparison period to switching circuits 11 to 14 as switching control signals S11 to S14. In the fine comparison period, one switching circuit is turned on, so that a fine comparison voltage is applied to voltage comparators 21 to 23. Since all of the switching circuits are turned off in a coarse comparison period, correct coarse comparison voltage is provided from a reference voltage generating circuit. As a result, a correct conversion in the coarse comparison period can be performed.

Abstract: The run length limited encoding/decoding system of this invention includes a clock swap logic circuit, a read reference clock multiplexer circuit, a write clock skip logic circuit, an encoder start logic circuit, an encoder circuit, a read clock skip logic circuit, a decoder start logic circuit, a decoder circuit, an input data buffer and a three-state output data buffer. The encoder circuit includes a deserializer for receiving serial data from a disk controller and blocking the data into m bit words. Each m bit data word is supplied directly to an encoding combinatorial logic circuit which in turn generates an n bit code word. The n bit code word is loaded in a serializer and serially transmitted out of the serializer. The decoder circuit includes a deserializer/serializer and a decoding combinatorial logic circuit. The deserializer/serializer receives a serial stream of encoded data and converts the data into n bit code words.

Abstract: An analog-digital converting device is designed such that when an operation of converting a special analog signal into a digital signal and an operation of converting another analog signal into a digital signal are instructed concurrently, priority is given to the conversion operation of the special analog signal, The analog-digital converting device includes an analog multiplexer having a main channel and a sub channel, a sample holder, an AD converter, a conversion result register having a plurality of storage areas, and an AD control circuit for controlling the drive of the individual components according to an instruction of a CPU. When the analog signals input to the channels are converted into digital signals in sequence, priority is given to AD conversion of the analog signal input to the main channel over AD conversion of the analog signal input to the sub channel.

Abstract: Improved apparatus and method for encoding and decoding information is disclosed herein. The invention uses the same marker segment information to engage an encoder or a decoder. The technique eliminates many of the complexities associated with building parameter lists, and generating various types of marker segments in a form compatible with both the decode and encode processing.

Abstract: A dual phase resolver to digital converter having two separate channels for generating rotor position data. The first channel generates an indication of rotor position based on a sinewave type reference signal applied to a first stator winding and the rotor signal while the second channel provides an indication of rotor position based on a cosinewave type reference signal applied to the second stator winding and the rotor signal. Logic circuitry associated with the data channels provide separate fault data indicative of when position data may be subject to error. The data from the two channels are selectively combined in the output of the converter. Data from one channel is used when the other channel is subject to fault. An average of the data is used when both channels are operating properly in order to provide greater accuracy.

Abstract: The present invention is directed to improvement of a differential amplifier an its peripheral components employed in an A/D converter to enhance an accuracy of the A/D converter. The differential amplifier has an amplifying element comprised of a pair of differential transistors Q1 and Q2, emitter resistances 2a and 2b, and collector resistances 2c and 2d. The differential amplifier has transistors Q3 and Q4 constituting an emitter follower for applying an output amplified in the differential amplifying element to the outside. The differential amplifier includes transistors Q5 and Q6 having their respective base electrodes connected to input terminals 4a and 4b and serially connected to the transistors Q3 and Q4, and resistances 2e and 2f interposed between emitter electrodes of the transistors Q5 and Q6 so as to relieve any influence of variations in base-emitter voltages of the transistors Q3 and Q4.

Abstract: A counter counts a clock signal. A multiplexer sequentially inputs digital input signals each having a plurality of bits in accordance with an output signal from the counter. A subtracter subtracts a quantized output signal delayed by an n-clock delay element from the input signal. An integrator integrates an output signal from the subtracter. The quantizer quantizes an output from the integrator. The n-clock delay element delays the output signal from the quantizer by n clocks and supplies the delayed signal to the subtracter. A demultiplexer sequentially outputs output signals from the quantizer in accordance with the output signal from the counter. This demultiplexer outputs signals in the input order of the multiplexer.

Abstract: A converter circuit provides analog to digital and digital to analog functions on a single silicon device. A flash analog to digital converter produces digital outputs using comparators which each receive an input signal and which each have different reference voltages. A decoder receiving digital inputs activates switches to connect selected ones of the same voltage references used by the flash analog to digital converter to a buffer which produces an analog output. The converter circuit can be a single or multi-stage flash analog to digital converter operating in a single channel or multi-channel environment. Timing and control logic prevents switching from occurring at times when perturbations on the voltage references could affect the analog and digital outputs.

Abstract: A analog-to-digital converter includes: an analog signal input, a reference voltage source, a portion for the combined processing of the analog signal and reference voltage, and a coding portion for supplying a digital output signal which is a function of the results of this processing. The processing portion includes at least one level of processing operators suitable for carrying out a non-linear calculation from their inputs; the coding portion include one level of output operators, each having as many inputs as there are outputs in the last level of operators in the processing portion. The transfer functions of the processing operators and output operators are chosen so as to allow an optimum analog-to-digital conversion over a given range of input signals.

Abstract: An A-D converter of an image signal comprises a weighing circuit for performing a different weighing for each quantization step of A/D conversion. The different weighing is performed in accordance with gamma or white compression characteristics of the image signal.

Abstract: A D-to-A converter of the type having a number of current sources each connected to a pair of switches operable by binary control pulses for directing the source current either to the output line or to ground. Power to operate the DAC is reduced by special control circuitry which opens both switches of any given switch pair whenever two successive control pulses call for the output-line switch to be open.

Abstract: A flexible data interface (21, 22) for a digital-to-analog converter (25, 26) includes a mute circuit (46, 70, 71 ) to mute and de-mute input data in 6 dB steps over a time period such as one-quarter of a second. The mute circuit includes a counter (46) to provide mute signals, a decoder (70) to decode the mute signals, and a shift matrix (71) to shift the data from zero to the maximum number of bits in response to the decoded signals. The interface (21, 22) includes a programmable shift register (43) to allow different data word lengths, such as 20-, 18-, or 16-bit, to be presented to the digital-to-analog converter (25, 26). The interface (21, 22) also includes a multiplexer (47) to allow left- and right-channel data to be received either time-multiplexed on a single pin, or on two separate pins.

Abstract: The preferred embodiment includes a method and apparatus for generating a comma code. A data word having a value m is received. A binary storage apparatus receives the data value. A storage apparatus is coupled to the output of the address calculator. The storage apparatus includes a plurality of single bit storage elements that are arranged to provide an M bit output. Each single bit storage element is initialized to a first value. The address calculator calculates the appropriate single bit storage element to be selectively inverted.

Abstract: A digital counting circuit, including a binary counter supplying output sals to an adjacent code encoder that processes the received signals and transmits its output to a binary decoder. The encoder has a plurality of D-type flip-flop devices to which selected outputs of the binary counter are connected. The circuit operates so that only one input change to the binary decoder is permitted for each change of count from the binary counter. This prevents any erroneous counts from momentarily appearing on the output lines of the binary decoder.

Abstract: An N-bit asynchronous successive approximation analog-to-digital converter is provided for converting an analog signal to a binary coded representation thereof. The analog-to-digital converter employs N inverting amplifiers. Each of the inverting amplifiers receives a scaled analog input signal and provides a one bit output of the binary coded output. The scaled analog input signal applied to each inverting amplifier includes an analog input signal and feedback signals from each of the inverting amplifiers which provide a more significant output bit of the binary coded output. Each inverting amplifier thereby provides an output dependent upon the amplifier's threshold voltage which output provides one bit of the binary coded representation. In addition, each inverting amplifier may further be adapted to receive a reference signal.

Abstract: A spur-free sigma delta modulator analog-to-digital converter for converting an analog input signal to a digital output signal is provided. A race Josephson junction is provided between the pulse generator and the integrating inductor. The race Josephson junction emits a voltage pulse in response to every sampling pulse. This voltage pulse kills any retained persisting current in the integrating inductor. By adding the race Josephson junction, nonlinearities in the converter are eliminated.A multiple flux quanta feedback generator for creating a multiple digital pulse feedback in response to an input signal is provided. A quantizer connected to the input inductor produces a pulse when the current produced by the input inductor exceeds a predetermined amount. A splitter is connected to the quantizer for producing output pulses. In order to produce 2.sup.n output pulses, 2.sup.n -1 splitters are required. Each of the splitters produces two output pulses in response to a single pulse produced by the quantizer.

Abstract: A sampling frequency converting apparatus includes an input port converting an input image data (X) into a data packet, a data driven engine executing interpolation on the data packet applied from the input port for performing sampling frequency conversion in which an operation is performed in accordance with a predetermined data flow program, an output port outputting the data packet produced by the data driven engine at a second sampling frequency, and an image memory for data processing. The sampling frequency converting apparatus can easily accommodate change of specification of the sampling frequency, and can be easily produced without requiring complicated timing control.