Abstract: An oversampled interpolative delta sigma analog-to-digital converter including a delta sigma modulator is provided with a cascade of bit-slice elements at the output of the modulator to form a filter/decimator. Each bit-slice element includes a filter circuit that filters the bit-rate signal in accordance with an arbitrary filter impulse response input signal to provide the converter with a filter characteristic that can be controllably varied without modifying the filter hardware. In each bit-slice element, an adder circuit and a delay circuit decimate the bit-rate signal produced by the delta sigma modulator to provide a digital output signal at a clock cycle rate equal to the Nyquist rate. The filter/decimator also provides encoding of the delta sigma output in 2's complement format.

Abstract: Signal sources are arranged in a matrix form and provide preset analog values. Switching means are connected between signal sources and an analog output terminal having connection paths to the respective signal sources. Latch circuits are respectively provided for switch control circuits for controlling the switching means. Each of the latch circuits latches a control signal from a corresponding one of the switch control circuits and outputs the control signal in response to a preset synchronizing signal to a corresponding one of the switching means. The switching means are simultaneously controlled by output signals of decoders so that a desired analog output is permitted to be derived from the output terminal. The period of the clock signal can be shorten and a switching operation causing variation exceeding a desired variation occurring when the digital signal is changed can be prevented.

Abstract: A medium-voltage circuit-breaker comprises a sealed enclosure filled with a dielectric gas and containing a semi-fixed first contact electrically connected to a first terminal and a mobile second contact electrically connected to a second terminal and mechanically coupled to an operating member. The semi-fixed contact is associated with a piston moving in a first cylinder constituting a first volume and provided at one end with a nozzle in which the mobile contact can be inserted when the circuit-breaker is in the engaged (on) position. The piston is acted on by a spring urging it in the direction in which the first volume decreases. The circuit-breaker comprises a system for causing the gas to circulate automatically between the first volume and a second volume when the current to be interrupted reaches a predetermined threshold value. The semi-fixed contact is a tube communicating with a third volume consisting of the remainder of the enclosure.

Abstract: A ground fault interrupter circuit is disclosed, comprising a high-voltage input from a public utility transformer, polarity reversal means coupled to the high-voltage input with polarity-switchable output coupled through a thyristor to a relay means. Radio frequency (RF) detection means are coupled to the thyristor gate, causing the thyristor to energize the relay and interrupt load power when radio frequency interference is detected from the load. The RF detector means comprises a plurality of RF chokes and resistor-capacitor pairs feeding a rectifier diode coupled to the thyristor gate. When RF is detected, the diode feeds negative direct current to the thyristor gate, interrupting conduction of the thyristor and the LOAD.

Abstract: A parallel operation power supply control system has a plurality of switching power supply modules for supplying electric power in parallel to a logic device, and a parallel operation power supply control module connected to a superior controller for control of the plurality of the switching power supply modules. Each of the plurality of the switching power supply modules comprises a DC-DC converter, a drive pulse generator for driving the DC-DC converter, and an electric current feedback unit for detecting an electric current outputted from the DC-DC converter and for feeding the detected result in the form of a first data to the parallel operation power supply control module.

Abstract: In a remotely controlled power supply, a switching element has a main switching section coupled to an input voltage source and an on/off control section responsive to an on/off switching signal. A main power supply includes an input side which receives main power from the source when the main switching section is in the closed position and an output side for supplying power to loads. An on/off decoder decodes a command signal having a plurality of states including a run state and a standby state to provide the aforementioned on/off switching signal. A standby power supply is coupled to the input voltage source for providing standby power to the on/off decoder during standby, whereas the switching element disconnects the main power supply from the source during standby. A second decoder decodes the other states of the command signal. The two decoders may be provided with separate system clock generators that are operated asynchronously of each other.

Abstract: A digitally controlled bit synchronizer and method for converting a pulse code modulated input signal having a known IRIG code into a filtered NRZ-L formatted output signal in phase with a predetermined clock signal. The bit synchronizer and method utilize a four-pole filter element, peak detector and reset circuits for removing AC offset, a variable controlled oscillator for adjusting the phase of the clock, Miller, Bi-Phase, and NRZ decoders, and a microprocessor for digitally controlling their operation and interconnection.

Abstract: A line protector for a communications circuit comprises a generally cup-shaped housing; and a generally disc-shaped solid state overvoltage arrester having electrodes formed at axially oppositely facing surfaces thereof for connection to a line circuit and a ground circuit respectively. An elongate contactor extends into the housing for contacting a first one of the electrodes and projects outwardly of the housing for contacting one of the line circuit and the ground circuit. An insulator member receives and positions the solid state overvoltage arrester with the other of the electrodes thereof in contact with a closed end of the cup-shaped housing and with the first electrode in position for contacting the contactor. An elastomeric member surroundingly engages the contactor and is surroundingly engaged by the cup-like housing for retaining the contactor, the insulator member and the overvoltage arrester in asembled condition within the housing.

Abstract: A lever assembly for the control of various electrical functions of a motor vehicle includes a hand operated control lever which is tiltable and rotatable with respect to and is supported by a base. A tension spring extends along a rotation axis of the control lever axis. One end of the spring is hooked to the control lever and the other end is coupled to the base, either directly or indirectly. The tension spring is hooked to a pin which is connected to the control lever and which simultaneously defines a tilt axis and forms part of a rotational stop mechanism.An arm of the control lever receives a plunger to which a contact of a horn operating switch element is attached. A pair of turn signal micro-switches are attached to the base and can be operated by rotation of the control lever. A third, central, dimmer micro-switch is operated by tilting the control lever to a detent position defined by a control gate which is attached to the base.

Abstract: An A/D conversion apparatus includes an analog input selecting device, and A/D converter and an operation control device. The operation control unit issues an input terminal designating signal to the analog input selecting device in accordance with an optionally designated A/D conversion order. Then, the analog input selecting device successively selects the analog input terminals in the designated order. The A/D converter A/D-converts the analog signals from the input terminals selected into digital values. In this way, the A/D conversion for the analog signals can be made in any priority, or the order of scanning the input terminals can be optionally set.

Abstract: The invented auto-ranging device has a signal measuring A/D converter, a range-switching A/D converter of a faster processing speed, a range-switching amplifier with variable amplification capabilities, and a processing controller which utilizes the variable amplification factors to alter the output signals from the switching A/D converter to generate signals appropriate for a scale range of a multi-range measuring A/D converter.

Abstract: An electric apparatus capable of using a plurality of power supplies includes a plurality of circuits which are fed with power from one of the plurality of power supplies. Switching circuitry is provided for controlling a sequence of power supplied to the plurality of circuits. Discrimination circuitry is provided for discriminating between the types of power supplies. Control circuitry then changes the sequence of supplying power in accordance with an output from the discrimination circuitry. Preferably, power is supplied to the plurality of circuits substantially simultaneously when a first power supply is used, but power is supplied to the plurality of circuits in a specified order when a second power supply is used. This prevents a power surge when a low-power power supply is used.

Abstract: In a communications system, input digital samples are continuously stored into a buffer and successively divided into a group of blocks of different lengths. The samples of each of the blocks are encoded into linear transform coefficients at intervals corresponding to the length of each block and each block of the linear transform coefficients is then decoded into a variable length block of decoded samples. An error between each block of decoded samples and a corresponding block of samples from the buffer is detected, and a plurality of such errors derived from each group of blocks of input samples are stored in memory. A minimum value of the errors in the memory is determined and one of the blocks of the coded symbols which corresponds to the minimum value is identified as having an optimum block length. The linear transform coefficients of the optimum block length are multiplexed with the optimum block length information into a channel for transmission.

Abstract: Apparatus for enhancing capacitance matching in a multi-stage capacitor network of an A/D converter is provided. The stages are coupled to one another by a coupling capacitor having a top and bottom plate. The apparatus comprises a first shield overlying the capacitor network, where the shield is coupled to a known potential. A second shield is positioned over each of the coupling capacitors, where each second shield is separate from the first shield and coupled to the bottom plate of each respective coupling capacitor.

Abstract: A low-noise switched-capacitor DAC converts an integer number from an N-bit digital format into an analog voltage level by transferring charge between two appropriately ratioed capacitors using a plurality of switches. The switches select only an appropriate one of a plurality of capacitors to connect to an operational amplifier in accordance with any digital input. The sampled kT/C noise and switch charge injection from an N-bit DAC is thus beneficially reduced.

Abstract: A programmable timer for turning a light on and off in response to changing sunset, daylight savings time, and other programmable conditions. The programmable timer includes an input device, a microprocessor, and a switch. The input device provides calendar, geographical, and daylight savings information to the microprocessor, which stores the programming information. The microprocessor computes an effective switching time from the stored information. The microprocessor employs program logic that compares the effective switching time to the current time to generate a timing control signal. The timing control signal, in turn, causes the switch to turn a light on and off. In the preferred embodiment, the microprocessor and the switch are included within a housing which mounts on a wall in place of a normal light switch. A liquid crystal display is disposed on a face of the housing to provide a read out of the programming information and of the time of day.

Abstract: A sampling frequency conversion apparatus according to this invention converts an input data string based on an input sampling pulse into a data string based on an output sampling pulse having a frequency different from the frequency of the input sampling pulse. The apparatus reproduces the input sampling pulse based on the input data string, generates interpolation sampling pulses having a frequency corresponding to an integral multiple of the frequency of the input sampling pulse, and generates an interpolated data string from the input data string on the basis of the interpolation sampling pulses. On the other hand, the apparatus phase-modulates the output sampling pulse to diffuse its frequency spectrum, and selects and determines a timing of the interpolation sampling pulse closest to the timing of the phase-modulated output sampling pulse. The apparatus selects data corresponding to the selected timing from the interpolated data string, and outputs the selected data.

Abstract: A self-aligning sampling system for sampling digital signals, for example in a logic analyzer includes an adjustable delay line fed by a system clock signal which delay line has tapping points for further clock signals. In conjunction with the system clock, the further clock signals are used to take several samples of the digital signal in a time slot of the system clock. In order to achieve equidistant sampling even in the case of a large process spread in elementary delay units of the delay line, the delay line is calibrated. The system clock is then connected to the data input and expressed in elementary delay units on the basis of measurement. Subsequently, the delay line between clock signal tapping points is adjusted on the basis thereof.

Abstract: In an A/D convertor, one comparator is provided for the most significant bit of the output digital signal, two for the second bit, and three each for the third and lower-order bits. When a compare operation is being performed by one of the three comparators that are provided for each of the third and lower bits, the remaining two comparators provide outputs in response to which output switch circuits perform setting of two reference voltages that are specified by the comparison result of a comparator corresponding to an output digital signal two bits higher.

Abstract: An analog-to-digital converter includes a delta-sigma modulator (10), having the output thereof filtered by a digital filter section. The digital filter section includes a first fixed decimation filter (12) followed by a variable decimation filter section (14) and an output low-pass filter section (16), having a fixed decimation ratio. The fixed variable decimation filter section (14) includes a single FIR filter (24) that has data processed therethrough with different sampling rates. A recursive controller (26) receives an external configuration input to determine the number of passes through the filter (24) that are required to provide the desired decimation ratio.