Abstract: A delta-sigma modulator is provided with a multi-stage shift register coupled to receive as its input the output from a quantizer including an analog integrator. The serial digital output signal train from the shift register is fed back to the input of the integrator and because of the frequency division which takes place, for a given high clock rate, an operational amplifier with a lower gain/bandwidth product may be employed. The invention also includes a signal processor coupled to the output of the delta sigma modulator and which is arranged to provide an adaptive window based, decimation cycle whose exact timing is data dependent. The adaptive windowing process implemented in a microprocessor-based signal processor allows the first occurrence of a proper polarity state transition occurring during a window period to become the termination point of the computation cycle rather than providing a fixed time interval.

Abstract: This invention relates to a video analog-to-digital converter (ADC) and to a method of digitizing a video analog signal. The video ADC (2) comprises a clock for providing a clock signal (HZ) which clocks a horizontal line rate, dither generating means (10) for generating a dither pattern synchronized with the horizontal clock signal. A preferred dither pattern comprises a staircase sequence of voltage steps, the voltage level of each step being constant for at least one horizontal line. The video ADC further comprises combining means for combining the dither pattern with the analog video signal, digitizing means (4, 6) for converting the combined dither pattern and video signal to a sequence of digital values and correcting means (12) coupled to the digitizing means and the dither generating means for subtracting the dither pattern from the digitized sequence of values so as to generate a sequence of digital values which represent said analog video signal.

Abstract: A class of lossless data compression algorithms use a memory-based dictionary of finite size to facilitate the compression and decompression of data. When the current dictionary (CD) fills up with encoded character strings, it is reset thereby losing the compression information previously contained in the dictionary. To reduce the loss in data compression caused by dictionary resets, a second, standby dictionary (SD) is used to simultaneously store a subset of the encoded data entries stored in the first dictionary. The data entries in the second dictionary represent the data entries of the first dictionary that compress the greatest amount of input data. When the first dictionary is ready to be reset, the first dictionary is replaced with the second dictionary, maintaining high data compression and freeing up memory space for new encoded data strings.

Abstract: A signal acquisition system using an ultra-wide time range digitizer with variable time interval data sampling and data storage includes signal conditioning and sampling stages, a digitizing stage for generating digital representations of a signal, and a memory for storing the digital representations. Timing circuitry controls sampling and digitizing which may be varied so as to acquire signals on linear, logarithmic, or other time bases. Signal compression may be obtained by digitizing information only when a desired change rate is observed. A display allows acquired signals to be displayed in linear, logarithmic or other manner.

Abstract: In recording systems using partial-response maximum-likelihood detection (PRML) techniques, data sequences are preceded by a preamble consisting of all ones. Coding schemes are disclosed which allow to keep the number of consecutive ones occurring in the coded data sequences at a minimum, while simultaneously restricting the number of consecutive zeros in full and partial data sequences to a low value which is important for improving receiver operation. The disclosed coding schemes and apparatus enable a faster and more reliable discrimination between timing preambles and data sequences, thus allowing to use shorter timing preambles which results in faster receiver start-up and in a reduction of storage overhead for the preambles.

Abstract: A delta sigma analog-to-digital architecture assures that all channels in a multi-element receiver follow the same compression and/or time-gain variation curve. This is accomplished by varying the reference voltage as a function of time so that the full scale range and associated quantization noise are large at the beginning of the receiving interval and become smaller as more distant echoes arrive. All channels follow the identical gain curve since all channels have the same reference voltage at the same time. The distribution of time-varying reference voltages may be done by using analog buses or by employing a timevarying digital code that specifies the reference voltages derived from a digital-to-analog (D/A) converter. In the latter case, corrections can be applied to the code at each channel.

Abstract: A position-encoded screw, and a method and system for calibrating a position-encoded screw. In one embodiment, the screw includes a threaded portion and a set of position-encoding marks arranged along a spiral path around the threaded screw portion. To calibrate the screw, a set of sensors detects each mark as the screw is incrementally advanced past the sensors, and the absolute position of the screw is independently measured using an auxiliary device such as a precision electro-optic scale. The output of the sensor set is processed to generate encoded position signals representing encoded displacements of the screw relative to a known position. A set of the independently generated absolute position signals, one corresponding to each encoded position signal, is stored in the form of a look-up table, so that each absolute position signal may be read from the table in response to a corresponding encoded position address signal.

Abstract: A method of signal processing batch-bulk coded digital signals which are segmented into variable-length words and the variable-length words are allocated to constant-length blocks. The constant-length blocks which receive a variable-length word having a word length which is shorter than a predetermined word length are filled up with portions of variable-length words having a word length longer than the predetermined word length. Several successive constant-length blocks are combined into superblocks, and one address word which identifies the superblock location is added at one end of each superblock. The sum of the variable-length words within each superblock is smaller than, or equal to, the sum of the constant-length blocks within the superblock.

Abstract: An equalization method is provided for compensating for variations in the characteristics of individual analog-to-digital converters found in a time interleaved analog-to-digital converter circuit. One of a plurality of converters is chosen as a reference converter. Individual characteristics of the remaining converters are compared with the reference converter to provide differential responses therewith. The differential responses are equalized to provide compensation for variations in gain, offset, phase/frequency response, and timing found amongst the plurality of time interleaved converters.

Abstract: A system provides I and Q baseband analog modulation signals for use in GMSK modulation responsive to serial bits of digital data. The I baseband modulation signal is represented by I(t)=cos [2.pi.f.sub.m .intg.g(t)dt] and the Q baseband modulation signal is represented by Q(t)=sin [2.pi.f.sub.m .intg.g(t)dt], wherein f.sub.m is the modulating frequency and g(t) is a filtered version of the serial bits of digital data. The system includes an input for receiving the serial bits of digital data, a memory including addressable memory locations for storing data representing the waveform amplitudes of the I and Q modulation baseband analog signals, and an address generator for addressing selected ones of the memory locations responsive to the serial bits of digital data. The system further includes digital to analog converters coupled to the memory for receiving the data stored at the memory locations addressed by the address generator and for converting the data to the I and Q modulation baseband analog signals.

Abstract: A capacitor array circuit is disclosed herein. A main capacitor array includes at least a most significant array portion 12 and a least significant array portion 14. A coupling capacitor C.sub.C is formed between the two portions of the array. Typically, one plate of the coupling capacitor C.sub.C is coupled to a top plate of each of the capacitors in the least significant array portion 14 and a second plate of the coupling capacitor C.sub.C is coupled to a top plate of each of the capacitors in the most significant array portion 12. A variable calibration capacitor C.sub.CAL is also provided. In a preferred embodiment, the variable calibration capacitor C.sub.CAL is coupled between the coupling capacitor C.sub.C and an AC ground node. In alternate embodiment, the variable calibration capacitor C.sub.CAL is coupled in parallel with the coupling capacitor C.sub.C. In the preferred embodiment, the variable calibration capacitor C.sub.

Abstract: A digital-to-analog converter (20) includes a linear interpolator (24) and a converter (25, 26) such as a sigma-delta modulator (25) and an associated analog summing network (26). The linear interpolator (24) includes a differentiator (200), an integrator (202), and a multiplexer (201). The differentiator (200) differentiates a received signal at a first rate. The multiplexer (201) multiplexes an output of the differentiator (200) to provide a multiplexed signal having a larger number of bits than the received signal in order to support multiple interpolating ratios. The integrator (202) integrates the multiplexed signal at a second rate to present to the converter (25, 26). By connecting the multiplexer (201) between the differentiator (200) and the integrator (202), the digital-to-analog converter (20) minimizes the size of the linear interpolator (24) while relieving a critical path between the linear interpolator (24) and the converter (25, 26).

Abstract: A solar battery system for a vehicle comprises a solar battery mounted on a body of the vehicle, a load connector for connecting selectively at least one of electric equipments provided in the vehicle with the solar battery so as to apply an output of the solar battery to the electric equipment connected thereby with the solar battery, a battery output checker for detecting the magnitude of the output of the solar battery, and a controller operative to select in response to the magnitude of the output of the solar battery detected by the battery output checker one or more of the electric equipments provided in the vehicle, which operate with power consumption corresponding appropriately to the output of the solar battery, as one or more electric equipments to be connected by the load connector with the solar battery.

Abstract: Apparatus 70 interfaces between port 20 of personal computer 10 and peripheral device 40 connectable to port 20. Transmit and receive data signals (TXD, RXD) are transmitted and received between port 20 and device 40 to pass through without substantial modification by apparatus 70. Protocol signals are transmitted by port 20 and processed to provide digital data signals. The protocol signals include a Request To Send (RTS) signal and a Data Terminal Ready (DTR) signal, whereby the apparatus processes RTS signal to provide a protocol clock signal and processes DTR signal to provide a protocol data signal. The protocol signals are monitored to identify a protocol signal pattern. Upon identifying such pattern within a particular protocol signal, a particular digital data signal is extracted from the protocol signal. The extracted digital data signal may then be converted to analog signals which are applicable to produce sound from speaker 80.

Abstract: A signal reproducing method comprising the steps of: inputting a reproduction signal of a signal which was encoded by a predetermined coding system; converting states of a plurality of portions of the waveform of the reproduction signal into numerical values in order to reproduce the input reproduction signal as the signal of a code train of "1" or "0"; and sequentially determining the portions as many as only the number specified by the coding system among the plurality of portions which were converted into the numerical values to be "1" on the basis of the magnitudes of the numerical values. By this arrangement, a signal reproducing method which can be reduced code errors of the reproduced signal may be provided.

Abstract: A sigma-delta digital-to-analog converter (20) reduces even order distortion, such as a DC offset, in an output signal by chopping the output signal alternately with set and reset pulses. The sigma-delta digital-to-analog converter (20) includes a sigma-delta modulator (25), a chop circuit (261) associated with a corresponding bit of the sigma-delta modulator (25), and an output buffer (264) for providing the output signal. The chop circuit (261) alternately inserts first and second logic levels into an output data stream of the sigma-delta modulator (25) before providing it to the output buffer (264). Even-order distortion is eliminated with only a tolerable attenuation of the output signal.

Abstract: An analog-to-digital converter (ADC) includes a capacitor array coupled to switches, an integrator stage connected to the switchable capacitors and a comparator stage connected to the output of the integrator stage. Means coupled to the comparator stage include a feedback loop to effectuate switching reference signals of opposite polarity for use during respective phases of operation of the ADC. The values of the capacitors can be programmed by the user of the ADC and switched to provide a desired total capacitance. For any fixed ratio of the input voltage to reference voltage, the duty cycle remains constant over a wide range of temperatures. Multiple stages afford large effective capacitor ratios with a small range of actual capacitance values and enable a reduction in silicon chip area for an ADC integrated circuit.

Abstract: An analog-to-digital converter converts multiple analog signals to multiple digital signals during a single conversion period. The converter comprises a multiple input integrator stage which provides an output voltage that is selectively compared to a multiplicity of voltages. The comparison voltages include reference voltages and additional signal inputs. A plurality of UP counters measure the number of clock pulses generated by a clock generator and enable the calculation of the output function.

Abstract: A system for data compression and decompression is disclosed. A series of fixed length overlapping segments, called hash strings, are formed from an input data sequence. A retrieved character is the next character in the input data sequence after a particular hash string. A hash function relates a particular hash string to a unique address in a look-up table (LUT). An associated character for the particular hash string is stored in the LUT at the address. When a particular hash string is considered, the content of the LUT address associated with the hash string is checked to determine whether the associated character matches the retrieved character following the hash string. If there is a match, a Boolean TRUE is output; if there is no match, a Boolean FALSE along with the retrieved character is output. Furthermore, if there is no match, then the LUT is updated by replacing the associated character in the LUT with the retrieved character.

Abstract: An irrigation controller is powered for all normal operations by light incident upon an 18 square inch photovoltaic module. Electrical power from the photovoltaic module is stored in high performance "super" capacitors. A transportable battery power source is connected to the controller to power its communication, such as for manual exercise and/or the loading of irrigation control programs. The external battery power source leaves the capacitor power storage recharged at the conclusion of each communication episode. The irrigation controller electronics, save for a real time clock that is updated, are not provided with a timing signal, and thereby consume almost no energy, save for brief millisecond sporadic time intervals of scheduled irrigation control. Capacitor power storage is approximately 6.5 mWH. Worse case photovoltaic energy production is 7.6 mWH daily. The sporadically operative irrigation controller uses less than 6.