Abstract: An Operational Analog to Digital (SYMAD) Convertor cell for converting an analog signal into a discrete binary code. An analog signal is processed by sample and hold circuitry and then compared to a reference voltage by a comparator. The comparator output is the converted digital output. This output is coupled back to the control input of an analog switch which selects either the reference voltage or a predetermined potential, typically zero volts, to couple to an inverting input of an operational amplifier. The analog signal input is also coupled to the non-inverting input of the operational amplifier. The operational amplifier is configured as a differential amplifier with a gain of two. If the digital output of the comparator is a logic 1, then the operational amplifier output is two times the difference between the analog signal and the reference voltage. If the digital output of the comparator is a logic 0, then the output of the operational amplifier is two times the analog signal.

Abstract: An electric power system having power supplies connected in parallel to a common bus includes a voltage feedback and current feedback loop for each supply. A voltage feedback signal and a current feedback signal are combined with a reference signal to produce an error signal. The output voltage of each supply is controlled in response to its corresponding error signal, to achieve current sharing and redundancy without interconnections among the control circuits of the various supplies.

Abstract: A digital-to-analog converter (DAC) is disclosed which uses an oversampled modulation technique followed by an analog lowpass filter to generate an output waveform with four precisely controlled amplitude levels for 2B1Q data transmission applications. The DAC accepts a 2-bit input word at the baud rate and generates one of four possible analog output amplitudes having relative ratios of +3, +1, -1, and -3.

Abstract: A general purpose programmable optical analyzer employs a nonlinear gain at the input stage of an analog to digital converter in order to limit the number of bits used to resolve shot noise.

Abstract: A two-loop superconducting sigma-delta analog-to-digital converter includes a first superconducting inductor to which the analog signal is applied. A resistor converts to current in the first inductor to a voltage which is applied to a second superconducting inductor. The current in the second inductor, which increases quadradically with time, is applied to an overdamped Josephson junction which kicks back a single quantum voltage pulse each time its critical current is exceeded. This pulse reduces the current in the second inductor and serves as a digital ONE output. The pulses are also applied to an underdamped Josephson junction in a feedback pulse generator which latches at its gap voltage for the remainder of a half cycle of an ac bias current.

Abstract: A precision sigma-delta analog-to-digital converter disposed to operate at a sampling rate giving rise to a relatively low oversampling ratio is disclosed herein. The high-order sigma-delta analog-to-digital converter (10) of the present invention is operative to convert an analog input signal to a digital output sequence. The inventive converter (10) includes a first integrating network (14) for generating a first sampled analog signal (X.sub.1) in response to the analog input signal. A second integrating network (18) generates a second sampled analog signal (X.sub.2) in response to the first sampled analog signal (X.sub.1). A third integrating network (22) generates a third sampled analog signal (X.sub.3) in response to the second sampled analog signal (X.sub.2). The sigma-delta converter (10) of the present invention further includes an internal quantizer (24) for generating the digital output sequence in response to the third sampled analog signal.

Abstract: A circuit for linearizing analog-to-digital output is shown in FIG. 2, with an analog signal V.sub.i transmitted by input circuit 10 is applied to an input port of an analog-to-digital converter 12 controlled by a sampling signal V.sub.s, to provide digital data V.sub.d on an "N" bit data bus 14. An analog-to-digital linearizing memory 16 storing a look-up table of digital values, is coupled to bus 14 to receive the digital data V.sub.d, and to respond to the digital data V.sub.d by providing true linear digital values from the look-up table to digital data processing system DSP 20 via an "N" bit data bus 18. A microprocessor 22 is temporarily coupled between the output port of converter 12 and the input port of memory 16 via bus 14, to serve as a switch between bus 14 and a programming memory 24 containing a table of true linear digital values V.sub.t. A known test signal is applied to input circuit 10, and true linear digital values V.sub.

Abstract: A partial word to full word parallel data shifter comprises 2N-1 multiplexer for selectively receiving data from the incoming current data word of width up to N, or from remainder bits of previously received data. The multiplexers output their data to 2N-1 latches, N of which output a full parallel data word and N-1 of which can recirculate up to N-1 remainder bits back to the multiplexers. If the number of remainder bits plus the number of data bits for the currently received word is less than N, the bits in the first N latches are not output but rather recirculate to the multiplexers where they are aligned for generating a full N bit output word with the most significant bit(s) of the next incoming parallel data.

Abstract: In an information data recording and reproducing device which can record and reproduce input information data accurately, an error correction code of the product sign format is added to the input information data to form coded data. The coded data are then NRZI converted and recorded onto a recording medium together with identification data of a predetermined data pattern. Error detecting and correcting are performed on data reproduced from the recording medium so as to obtain the data recorded on the recording medium.

Abstract: An electronic automatic energizing damping device for connection to a source of electrical energy to protect and safeguard continuously all the devices, instruments, equipment and systems, connected to the source. The device comprises a control stage and a power stage. The control stage monitors the operating conditions of both the A.C. line and the load energized by it via the power stage, in order to detect irregularities in any of the programmed parameters of the voltage or the current, and supplies control signals that regulate the power stage. The power stage supplies the energy of the network to the load, according to the commands of the control stage. The control stage features a voltage sensor circuit, a current sensing circuit, a comparison circuit to receive the output of the voltage sensor circuit and an energy relay control circuit. The power stage comprises a surge breaker and suppressor, and an optical interface circuit.

Abstract: A control apparatus for an electromagnetic device having a proportional solenoid has a duty factor calculation circuit for calculating a duty factor on the basis of a control target value, a pulse signal formation circuit for forming a pulse signal based on the calculated duty factor, an exciting current formation circuit for forming an exciting current for electrically stimulating the coil of an electromagnetic apparatus in response to the formed pulse signal, and an integration circuit for integrating the exciting current of the coil in synchronization with the pulse signal. This control apparatus calculates the duty factor using the duty factor calculation circuit from a control target value and the integration value output from the integration circuit.

Abstract: The anomaly handling facility provides a system for controlling conversion, detecting anomalies, providing analysis of anomaly content in an array of floating-point elements, and preserving reconstruction data to recover value accuracy typically lost when anomalies are encountered during conversion.Although the preferred embodiment specifically handles anomalies relative to the commonality of value representation by both IBM ESA/370 hexadecimal floating-point notations and ANSI/IEEE 754-1985 binary floating-point stand notations, the systematic design provided by the disclosed floating-point notation conversion anomaly handling facility can be applied to an pair of floating-point notation systems that are not totally coincident in value coverage.

Abstract: Method and apparatus for directly converting the value of an analog signal into a digital format for a prespecified number system. For analog to digital residue number conversion, a plurality of residue channels convert the analog value to a set of digitized residues corresponding to a prespecified set of residue bases.

Abstract: A technique for correcting settling, feedthru, and higher order error mechanisms in a dithered analog-to-digital conversion circuit is disclosed. For each conversion cycle of an ADC, a dither signal is generated by converting a current dither value from a sequence of dither values and is then added to an analog input signal. The analog input signal and dither signal are converted by the ADC, and the current dither value subtracted, to form a digital output signal. Correction signals proportional to dither values which precede or follow the current dither value in the sequence are also generated each conversion cycle and subtracted from the analog input signal. The proportions used to produce the correction signals are adjusted dynamically according to the amount of correlation between the digital output signal and the dither values used to form the correction signals. The correction signals are thereby made to equal the amount of error contributed by a corresponding one of the error mechanisms.

Abstract: A symmetric pipelined charge-mode analog to digital converter including a signal-reference CCD channel having a plurality of charge storage stages that are arranged in a serial configuration to carry the signal and reference charges, and a CCD digital channel. A set of two step comparators coupled to the signal-reference channel first senses and stores the signal charge and then senses and compares the reference charge to the signal charge. In the first stage, an initial reference charge is used, and in subsequeant stages, an increment of one half the previous stage increment is added to the reference. In addition, at each stage, a charge increment equal to the previous reference increment is conditionally added to the signal charge and a corresponding bit in the digital channel is conditionally set responsive to the comparator.

Abstract: The disclosed circuit for actuating headlights has two time delay circuits, an AND gate, a power relay, and connections for appropriate installation to the circuitry of the automobile. When windshield wipers are operated, a pulse of the windshield wiper motor causes the first time delay circuit and the second time delay circuit to run timing cycles. The timing cycle of the first circuit is shorter than the timing cycle of the second circuit, and the first circuit is restarted with each pulse of the windshield wiper motor. Each timing delay unit has an output signal which is a logical "one" when a cycle is being run and a logical "zero" when a cycle is not being run. When the AND gate receives logical zeros from the second time delay circuit, and logical ones from the first time delay circuit, windshield wipers are in use and the headlights and parking lights are switched on. A daylight detection circuit may be incorporated to provide safe use of the unit in dusk hours.

Abstract: A delta sigma analog-to-digital (A/D) converter includes a digitally-controlled multiplying digital-to-analog converter (MDAC) in a feedback configuration. The MDAC is driven by a digital signal obtained from the output (or an intermediate output) of the A/D converter. An incremental feedback quantum to the first stage integrator is a function of the input values that immediately precede it. In the most general implementation, a table look-up permits an arbitrary relation between the input values and feedback quantum size. In another implementation, the A/D converter output (or intermediate output) signal drive the MDAC and the compression curve of the A/D converter bears a square-root relationship to the input analog signal; a linear relationship is restored by squaring the output signal. In a third implementation, the MDAC is driven by a digital signal obtained from the output (or an intermediate output) of the A/D converter together with an added small positive constant number.

Abstract: A switch device for use in a power window for opening and closing a door glass of a vehicle. The switch device is driven by a driving apparatus and has a display unit for displaying whether the door glass can be opened or closed by means of an operating switch via the driving apparatus. Accordingly, it is possible to visually confirm whether or not the driving apparatus can be driven.

Abstract: A split core degaussing coil loop having a segmented and disassembled loop portion that is joined together to include an object to be demagnetized, in situ, as part of the assembled core loop and further having an inductor coil assembled with the loop that is selectively energized in one or more steps from a source of electrical power which generates a demagnetizing force directed to the object.

Abstract: In a CMOS DAC having a plurality of stages a control circuit for selectively switching said DAC between a sleep mode and a normal operating mode with little, if any, surge current resulting therefrom. In the control circuit there is provided control transistors responsive to control signals for applying a reverse biasing potential to a reference voltage transistor and a digital input transistor in each of the stages at a rate such that the rate of change of current in the reference voltage transistor is less than a predetermined magnitude, e.g. less than 5 ma/nsec. when said DAC is switched to its sleep mode and transistor means responsive to control signals for first applying a predetermined forward biasing potential to a bias transistor and thereafter changing said reverse potential applied to said reference voltage transistor to a predetermined reference voltage and removing said reverse bias potential from said digital input transistor when said DAC is switched to its normal operating mode.