Abstract: A high-performance superconducting analog-to-digital (A/D) converter providing high-speed, high-resolution A/D conversion with low power consumption. The superconducting A/D converter of the present invention includes a bidirectional binary counter having n stages of triple-junction reversible flip-flops, where n is the number of bits of the digital output, and a pair of superconducting inductors for inductively coupling an analog input current to the bidirectional counter. The bidirectional counter algebraically counts incremental changes in the analog input current, increasing the binary count for positive incremental changes in the analog current and decreasing the binary count for negative incremental changes in the analog current. The bidirectional counter requires no gate bias, thus requiring minimal power for operation.

Abstract: A system is provided for converting an input digital data sampled at a first sampling frequency to an output digital data to be sampled at a second sampling frequency. The input digital data is sampled to obtain sampling data with respect to an estimating data corresponding to a data at a sampling point of the output data. The sampling is performed within a period of the least common multiple between a period of sampling of the input digital data and a period of sampling of the output digital data. The estimating data is interpolated from the obtained sampling data.

Abstract: The K most frequently occurring symbols in an image represented by an alphabet of N symbols are mapped to a set of K codewords. The length of each codeword is an inverse function of the frequency of occurrence of the corresponding symbol in the image and the longest codeword is of length d bits. The remaining N-K symbols are mapped in order of their magnitude to a set of supplementary codewords of a uniform maximum length D bits. The d most significant bits of each supplementary codeword form a prefix which is uniform within each set and specifies whether the corresponding symbol is positive or negative. The remaining or least significant D-d bits of each supplementary codeword comprise a suffix and are mapped in order of bit position to progressively more narrow ranges of symbol values of the remaining N-K symbols.

Abstract: A combined optical and capacitive absolute positioning encoding system uses a plurality of metallized strips deposited onto a glass scale substrate. A movable transceiver is positioned adjacent to the scale. The transceiver generates interrogating electrical an optical signals which interact with the scale. The movable transceiver also carries with it receiver mechanisms for receiving the signals after interaction with the scale. Signal processing electronics are provided to determine the relative positions of the scale and transceiver by comparing the transmitted, interrogating signals with the received signals. The system is able to determine the relative positions of the scale and transceiver even if power to the system is interrupted, or if the scale and transceiver are moved relative to one another very rapidly.

Abstract: An A/D converter includes a resistor network generating a reference voltage, a level detector for detecting the level of an input analogue signal with a reference voltage from the resistor network as a reference, and an encoder for providing a digital signal by encoding the output of the level detector. The level detector includes a plurality of comparators for bilevel-processing the input analogue signal with a preselected voltage from the resistor connection nodes of the resistor network as a reference voltage. The resistor network comprises a plurality of resistor elements between a first node receiving a first reference voltage and a second node receiving a second reference voltage, which are interconnected to provide a voltage from an associated connection node that is 1/2.sup.j times the difference between said first reference voltage and said second reference voltage.

Abstract: A method of encoding the characters of a character set, wherein the characters have a plurality of attributes (e.g., base, diacritical, and case), and wherein each attribute may have a plurality of values. The method comprises the steps of: dividing a multi-digit code into a plurality of parts, assigning each attribute to a different part, and, within each part, assigning a different numerical code to each different value of the attribute.

Abstract: A serial-parallel converting circuit comprises a four-stage shift register circuit receiving a serial data so as to shift the received serial data through the shift register in response to each clock signal, and an output register circuit coupled in parallel to respective stages of the shift register circuit so as to fetch the content of the shift register circuit in response to a frequency-divided clock supplied from a frequency dividing circuit. The frequency dividing circuit receives the clock signal through an inverter and is composed of only two D-type flipflops and one inverter. Each of the D-type flipflops has a clock input connected to receive the clock signal in common, and the D-type flipflops are connected in series to form a shifter register. A Q output of a second flipflop is connected through the inverter to a data input of a first flipflop, so that the Q output of the last flipflop generates the frequency-divided signal.

Abstract: Efficient decoding of an hierarchical, variable length, encoded data sequence containing embedded uncoded data into a sequence of fixed length instructions for subsequent processing by a digital video processor or the like is realized in an apparatus including a decoder having a plurality of variable length code decoding elements and a control structure embedded within each decoding element for transferring the decoding operation to an appropriate one of the decoding elements in response to a prior output from the decoder element. As the encoded data sequence is processed by the apparatus, a predetermined length of the sequence is stored in a register. The control structure further responds to the encoded data sequence to initiate selection of either the predetermined length of the sequence stored in the register or a portion of the decoder output as the fixed length instruction to be output by the apparatus.

Abstract: A digital-to-analog converter (20) with improved performance includes an offset/scaler (23), a sigma-delta modulator (25), and an analog summing network (26). In one embodiment, the offset/scaler (23) scales an input signal by a predetermined amount, such as three-quarters, to compensate for nonlinearities in a transfer characteristic of the sigma-delta modulator (25). In another embodiment, the sigma-delta modulator (25) is a sufficiently-resolved sigma-delta modulator. The offset/scaler (23) provides an offset to the sufficiently-resolved sigma-delta modulator (25) sufficient to force a coarse bit thereof into an idle pattern.

Abstract: An analog-to-digital converter (ADC) has at least one resistance ladder circuit for generating a stepped series of reference voltages and set of comparator circuits for comparing an input voltage, or a voltage derived therefrom, with at least a subset of the stepped series of reference voltages. A memory array embedded in the ADC stores a digital value corresponding to each tap point of the resistance ladder and thus to each reference voltage. During a first conversion cycle an estimated conversion value is generated based on comparison of the input voltage with the stepped series of reference voltages. The estimated conversion value corresponds to one of the resistor ladder tap points selected as being closest in voltage to the input voltage. In a second conversion cycle, a derived voltage based on the input voltage of the estimated conversion value, is compared with a smaller range of reference voltages to generate a finer resolution conversion value.

Abstract: A D/A converter comprises a bias circuit including a series circuit of a drain-source of a bias FET and a bias resistor connected between a power source terminal and a reference potential point, the bias circuit includes a negative feedback amplifier to which a reference voltage is supplied, a digital to analog converting section includes a plurality of constant-current source FETs having a current value substantially equal to the current value of the bias FET of the bias circuit, and includes a plurality of current switches for selectively supplying currents of the constant-current source FETs to an output terminal in response to a digital input signal. An output resistor with resistance value Ro is connected to the output terminal to produce an analog output voltage across the output resistor and the resistance of the bias resistor is varied so as to adjust the full scale voltage across the output resistor while maintaining the relationship that the resistance value of the bias resistor is selected by (2.

Abstract: A binary data converter is adapted to convert a positive binary data into a negative binary data represented by a complement on two and vice verse. The conversion is effected as follows. A least significant bit of an inputted binary data is outputted as the least significant bit of the converted binary date as it is. With respect to bit signal other than the least significant bit, respective input bit signals less significant than the corresponding input bit signal are ORed. Depending on the result thereof, inverted or non-inverted signals of the corresponding input bit signals are outputted as the bit signals of the converted binary data. Therefore, carry delay is not generated, and thus the operation speed can be increased. Further, the simple circuit structures can reduce the number of required elements.

Abstract: An integrating analog-to-digital converter comprising an integrator, a memory capacitor for memorizing the potential of an integrated output from the integrator, a comparator for comparing the potential memorized in the memory capacitor and the potential of the integrated output divided by a set of potential dividing resistances, a clock pulse generating circuit, a counter for counting the period until the integrated output of the reference voltages passes through a reference level using clock pulses, and a reversible counter for counting the period from when the integrated output passes through the reference level to when the integration is completed, by the clock pulses, and for adding its value to the counted value from the counter as low order digits; wherein the number of digits of AD conversion is increased, and high conversion accuracy and high resolution are realized by enlarging the time period from the reference level crossing point to a clock pulse immediately after the crossing in the reference vo

Abstract: A decoder/encoder apparatus is provided which can be programmed to decode data and to encode data. To encode data, a memory within the apparatus is preloaded with a first memory map which is descriptive of a selected tree-based binary code. The first memory map is a reverse tree representation of the selected tree-based binary code. Data is then provided to the apparatus and is processed as specified by the first memory map thus generating encoded data. To decode data, the same memory is preloaded with a second memory map which is descriptive of the same selected tree-based binary code. The second memory map is a tree representation of the same selected tree-based binary code. Encoded data is then provided to the apparatus and is processed as specified by the second memory map thus generating decoded data.

Abstract: A data latch circuit of a delta sigma modulator is controlled in timing of data output by clock signal. For this purpose, the data latch circuit has a reverse phase clock input terminal connected to a first delay circuit and a forward phase clock input terminal connected to a second delay circuit. The latch circuit is composed of two P-MOS transistors and two N-MOS transistors. The delay times of the first and second delay circuits are coincided, and those of the respective two P- and N-MOS transistors are also coincided.

Abstract: A cyclic analog-to-digital converter includes two arithmetic circuits and a single comparator. The output of each arithmetic circuit is connected to the input of the other arithmetic circuit. Each arithmetic circuit can modify the analog signal being converted in accordance with output signals from the comparator. Embodiments are disclosed in which the arithmetic circuits include switched capacitors and separate or shared operational amplifiers.

Abstract: An analog-to-digital converter (ADC) having two cascaded A/D stages of the parallel type wherein the analog signal is compared with a set of threshold reference voltages. The first stage develops a set of most-significant bits and produces two analog residue signals: a normal residue corresponding to the difference between the analog input and the threshold voltage below the analog input, and a second residue corresponding to the difference between the analog input and the threshold voltage above the analog signal level. These two residue signals are amplified and directed to the second A/D stage. The sum of the residue signals equals one LSB of the first A/D stage, so that the two residues supply to the second stage information about the quantization error of the previous stage as well as the quantization step size to be used to define full-scale at the second stage.

Abstract: A method and apparatus for real time processing of digitally encoded pattern information suitable for distributing such information to a large number of individual pattern applicators which are grouped into a number of successive arrays. When applied to a patterning process involving the selective application of dye streams to a moving substrate, the disclosed real time processing includes transforming pattern data to corresponding dye contact times, resequencing the transformed data to compensate for physical spacing between arrays, and converting the resequenced data to logical dye stream contact commands to be sent to the individual applicators.

Abstract: This invention relates to a digital modulating method used for recording a PCM audio signal, computer data, and etc. on a recording medium such as an optical disc. The digital modulating method is constructed so that the minimum length between transition could be the maximum in encoding M bits into N bits (M<N), and can generate clock pulses with a simple circuit arrangement by satisfying the relationship N=.alpha.M, where .alpha. is an integer equal to or larger than 2.Further, by converting a predetermined unit of input data into a first code signal according to substantially the same conversion rule and selectively adding coupling bits of different bit number to each junction between a first code signal and an adjacent code signal, the digital modulating method is adaptable for various transmission systems with a simple arrangement.

Abstract: A circuit arrangement for converting a digital signal of a first frequency into a signal of a second frequency and including an interpolator/decimator is characterized, notably for asynchronous first and second clock signals, in that there is provided at least one multiplexer arrangement which includes a first register which is clocked at the inverted first clock frequency and a second register which is clocked at the second clock frequency, and also includes a multiplexer, the input signal of the multiplexer arrangement being applied to the first register and to a first input of the multiplexer whose second input is coupled to the output of the first register, there also being provided a control circuit which alternately switches the signals applied to the two inputs of the multiplexer to its output in such a manner that at the instants at which this signal is written into the second register a valid signal is always present at the output of the multiplexer.