Abstract: A transistor comprises a channel region between a source region and a drain region, a dielectric material adjacent to the channel region, an electrode adjacent to the dielectric material, and an electrolyte between the dielectric material and the electrode. Related semiconductor devices comprising at least one transistors, related electronic systems, and related methods are also disclosed.

Abstract: An integrated circuit package includes a transmission line structure, conductive bonds, a post and a dielectric post. The transmission line structure runs from a printed circuit board (PCB) to an integrated circuit (IC) and includes a center transmission line surrounded by ground and sealed from exposure to air. The conductive bonds connect the transmission line structure to pads on the integrated circuit from where the center transmission line exits the integrated circuit package. The first post is part of the center transmission line where the center transmission line enters the integrated circuit package from the printed circuit board. The dielectric post supports the center transmission line where the center transmission line exits the integrated circuit package to connect to the conductive bonds and compensates part of the conductive bond inductance.

Abstract: Systems and methods are described for a white light emitting module that emits a third white light with the goal of providing human-friendly illumination. The white light emitting device comprise a first light emitting package that emits a first white light and a second light emitting package that emits a second white light. The first light emitting package includes a first light emitting device and a filter member that filters light emitted from the first light emitting device and then reduces a color temperature of the first white light. The second light emitting package includes second and third light devices. The color temperature of the first white light is about 1,500 K to about 4,000 K. A color temperature of the second white light is about 3,000 K to 10,000 K.

Abstract: A flexible display device includes a substrate, a plurality of first pixels, and a plurality of second pixels. The substrate includes a foldable bending region and a non-foldable non-bending region. Each first pixel is disposed on the bending region. Each first pixel is spaced apart from an adjacent first pixel by a first distance. Each second pixel is disposed on the non-bending region. Each second pixel is spaced apart from an adjacent second pixel by a second distance. The first distance is greater than the second distance.

Abstract: A method of fabricating a display panel having a display area and a component installation area substantially surrounded by the display area. The method includes forming one or more organic layers on a base substrate in both the display area and the component installation area; removing the one or more organic layers in at least a first region of the component installation area; forming an encapsulating material layer in at least the first region of the component installation area; and curing the encapsulating material layer.

Abstract: An organic light emitting diode display panel includes a base substrate; a pixel definition layer for defining a plurality of subpixels on the base substrate; a plurality of organic light emitting diodes respectively in the plurality of subpixels; and a first inorganic encapsulating layer between the base substrate and the pixel definition layer configured to encapsulate the plurality of organic light emitting diodes in the plurality of subpixels. The pixel definition layer includes a plurality of pixel definition blocks spaced apart from each other. The first inorganic encapsulating layer includes a plurality of first inorganic encapsulating blocks, each of the plurality of first inorganic encapsulating blocks is between the base substrate and one of the plurality of pixel definition blocks and configured to encapsulate one of the plurality of organic light emitting diodes in one of the plurality of subpixels.

Abstract: The embodiments of the present disclosure provide a display panel, a method for manufacturing a display panel, and a display apparatus. The display panel includes a hole located in a display area of the display panel and penetrating the display panel, and an isolation structure located around the hole and partially penetrating the display panel, wherein a heat resistance of a material of the isolation structure is greater than that of a material adjacent to the isolation structure.

Abstract: The present disclosure relates to an array substrate and a method for manufacturing the same. The array substrate includes a substrate having first regions for forming pixels and second regions located between the first regions, light shielding portions located within portions of the second regions adjacent to the first regions on the substrate, and pixel defining portions located within the second regions. At least a side surface of the light shielding portion adjacent to the first region is not covered by the pixel defining portion.

Abstract: A first fin structure is disposed over a substrate. The first fin structure contains a semiconductor material. A gate dielectric layer is disposed over upper and side surfaces of the first fin structure. A gate electrode layer is formed over the gate dielectric layer. A second fin structure is disposed over the substrate. The second fin structure is physically separated from the first fin structure and contains a ferroelectric material. The second fin structure is electrically coupled to the gate electrode layer.

Abstract: An electro-optical device includes a pixel electrode having translucency, a wiring layer including a translucent portion having translucency configured to overlap the pixel electrode in plan view in a thickness direction of the pixel electrode, and a wiring portion including a plurality of wirings arranged in a periphery of the translucent portion in the plan view, an insulating layer arranged between the pixel electrode and the wiring layer, and including a lens surface having a curved shape, a lens layer having translucency arranged between the pixel electrode and the insulating layer, and arranged on the insulating layer to be in contact with the lens surface, a first mark formed of a same layer as a part of the plurality of wirings of the wiring layer, and a second mark arranged in contact with the insulating layer on the lens layer side as viewed from the insulating layer.

Abstract: An organic light emitting display panel includes a cover plate and a back plate. The cover plate includes a cover plate glass on which three color films of R, G and B are formed. The cover plate includes an insulating cover layer covering the cover plate glass. The cover plate includes a BM area formed over the insulating cover layer and defining a pixel area. The cover plate includes a spacer pillar formed in the BM area. The cover plate includes an auxiliary cathode formed over the spacer pillar and the insulating cover layer. The back plate includes: an active layer array; a planarization layer formed on the active layer array, having a boss corresponding to the pixel area; and an OLED device formed on the boss.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, one or more peripheral devices on the substrate, a plurality of NAND strings above the peripheral devices, a single crystalline silicon layer above and in contact with the NAND strings, and interconnect layers formed between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.

Abstract: A finned semiconductor structure including sets of relatively wide and relatively narrow fins is obtained by employing hard masks having different quality. A relatively porous hard mask is formed over a first region of a semiconductor substrate and a relatively dense hard mask is formed over a second region of the substrate. Patterning of the different hard masks using a sidewall image transfer process causes greater lateral etching of the relatively porous hard mask than the relatively dense hard mask. A subsequent reactive ion etch to form semiconductor fins causes relatively narrow fins to be formed beneath the relatively porous hard mask and relatively wide fins to be formed beneath the relatively dense hard mask.

Abstract: A photodetector disclosed herein includes an N-doped waveguide structure defined in a semiconductor material, wherein the N-doped waveguide structure comprises a plurality of first fins. Each adjacent pair of the plurality of first fins is separated by a trench formed in the semiconductor material. The photodetector also includes a detector structure positioned on the N-doped waveguide structure, wherein a portion of the detector structure is positioned laterally between the plurality of first fins. The detector structure comprises a single crystal semiconductor material. The photodetector also includes a first diffusion region that extends from the bottom surface of the trench into the semiconductor material, wherein the first diffusion region comprises atoms of the single crystal semiconductor material of the detector structure.

Abstract: Embodiments of the present invention are directed to forming a Resistive Random Access Memory (RRAM) device with a spacer for electrode isolation. In a non-limiting embodiment of the invention, a memory stack including a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode is formed. A portion of the memory stack is removed to expose a sidewall of the top electrode and a spacer is formed on the sidewall of the top electrode. The spacer is positioned to encapsulate the top electrode, physically preventing a short between the top electrode and the bottom electrode.

Abstract: A light-emitting display device includes a pixel defining layer with an opening that exposes a first electrode, a hole injection layer on the first electrode, a lyophilic pattern on the hole injection layer in the opening, a hole transport layer on the lyophilic pattern, a light-emitting layer on the hole transport layer, and a second electrode on the light-emitting layer. The lyophilic pattern includes a first part adjacent to a first sidewall of the opening and a second part adjacent to a second sidewall of the opening. A distance from a top surface of the hole injection layer to an edge of a top surface of the second part corresponds to a first height. A distance from the top surface of the hole injection layer to a top surface of the first part corresponds to a second height. The first height is lower than the second height.

Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first barrier layer is formed on the gate dielectric layer, a second barrier layer is formed on the first barrier layer, a first work function adjustment layer is formed on the second barrier layer, the first work function adjustment layer and the second barrier layer are removed. After the first work function adjustment layer and the second barrier layer are removed, a second work function adjustment layer is formed over the gate dielectric layer, and a metal gate electrode layer is formed over the second work function adjustment layer.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory comprises a first variable resistance element coupled between a first wiring and a second wiring, the first variable resistance element including a first variable resistance layer having a first width at a first distance from the first wiring; and a second variable resistance element coupled between the second wiring and a third wiring, the second variable resistance element including a second variable resistance layer having a second width at the first distance from the second wiring. The first width is greater than the second width.

Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.

Abstract: A manufacturing method of a semiconductor device includes the following steps. An opening is formed penetrating a dielectric layer on a semiconductor substrate. A stacked structure is formed on the dielectric layer. The stacked structure includes a first semiconductor layer partly formed in the opening and partly formed on the dielectric layer, a sacrificial layer formed on the first semiconductor layer, and a second semiconductor layer formed on the sacrificial layer. A patterning process is performed for forming a fin-shaped structure including the first semiconductor layer, the sacrificial layer, and the second semiconductor layer. An etching process is performed to remove the sacrificial layer in the fin-shaped structure. The first semiconductor layer in the fin-shaped structure is etched to become a first semiconductor wire by the etching process. The second semiconductor layer in the fin-shaped structure is etched to become a second semiconductor wire by the etching process.