Abstract: Some embodiments include an integrated assembly having an access transistor. The access transistor has a first source/drain region gatedly coupled with a second source/drain region. A digit line is coupled with the first source/drain region. A charge-storage device is coupled with the second source/drain region through an interconnect. The interconnect includes a length of a semiconductor material. A protective transistor gates a portion of the length of the semiconductor material.

Abstract: A display apparatus includes a substrate, a display area disposed on the substrate and including a plurality of pixels, a first planarization layer disposed on the substrate, a second planarization layer disposed on the first planarization layer, a pixel-defining layer disposed on the second planarization layer and covering at least one edge of a first electrode of each of the plurality of pixels, a plurality of first holes disposed between the plurality of pixels and spaced apart from the first electrode, and a first etching prevention layer disposed on a bottom surface of each of the first holes and on the first planarization layer. Each of the first holes includes an opening that passes through the second planarization layer and the pixel-defining layer.

Abstract: A light emitting display apparatus includes a substrate including a plurality of sub-pixels, each of the plurality of sub-pixels including a light emitting area and a reflective area surrounded by the light emitting area, an overcoating layer on the substrate, a partition at the reflective area on the overcoating layer, a light emitting element at the light emitting area on the overcoating layer, and a reflective part on the partition and formed of a same material as the light emitting element.

Abstract: A semiconductor package in an aspect of the present invention includes a metal board, a first frame, a second frame, and a bond. The metal board has an upper surface including a mount on which a semiconductor device is mountable. The first frame has a side surface facing a side surface of the metal board and has a smaller thermal expansion coefficient than the metal board. The second frame is on upper surfaces of the metal board and the first frame and surrounds the mount, and has a smaller thermal expansion coefficient than the metal board. The bond is between the metal board and the first frame, between the metal board and the second frame, and between the first frame and the second frame. The semiconductor package includes an alloy layer between the metal board and the bond.

Abstract: An encapsulation cover for an electronic package includes a frontal wall with a through-passage extending between faces. The frontal wall includes an optical element that allows light to pass through the through-passage. A cover body and a metal insert that is embedded in the cover body, with the cover body being overmolded over the metal insert, defines at least part of the frontal wall.

Abstract: An illustrative device disclosed herein includes a semiconductor substrate. The substrate includes a source region, a drain region and a channel region. The channel region is arranged between the source region and the drain region. A gate insulation layer is provided over the channel region. A floating gate electrode is provided over the gate insulation layer. A layer of a ferroelectric material is provided over the floating gate electrode. A top electrode is provided over the layer of ferroelectric material. A projected area of the top electrode onto a plane that is perpendicular to a thickness direction of the semiconductor substrate is smaller than a projected area of the floating gate electrode onto the plane.

Abstract: A device includes a substrate including a display area and a pad area; a first conductive layer on the substrate; and a first insulating film on the first conductive layer, the first insulating film having a first contact hole in the display area to expose the first conductive layer and a pad opening exposing the first conductive layer in the pad area, the first conductive layer being arranged such that in a first region covered by the first insulating film, a second conductive capping layer of the first conductive layer is entirely on a first conductive capping layer of the first conductive layer; in a second region overlapping the contact hole, the second conductive capping layer is entirely on the first conductive capping layer; and in a third region exposed by the pad opening, the second conductive capping layer exposes at least a portion of the first conductive capping layer.

Abstract: The present disclosure provides a flexible display device including a substrate, a first metal layer, a first insulating layer and a second insulating layer. The substrate includes an active region and a peripheral region adjacent to the active region. The first metal layer is disposed on the substrate. The first insulating layer is disposed on the first metal layer, and the first insulating layer includes a first via hole disposed in the peripheral region. The second insulating layer is disposed on the first insulating layer, and the second insulating layer includes a second via hole. In a top view direction of the flexible display device, the first via hole is disposed within the second via hole, and the second via hole exposes a portion of a top surface of the first insulating layer.

Abstract: A display device includes a substrate including a first display area and a second display area, the first display area including a first pixel, and the second display area including a second pixel and a transmissive area, a first pixel electrode and a first emission layer in the first pixel, a second pixel electrode and a second emission layer in the second pixel, an opposite electrode arranged as one body in the first display area and the second display area, and a top layer arranged on the opposite electrode, wherein the opposite electrode and the top layer each have an opening area corresponding to the transmissive area, and wherein a convex portion is around the transmissive area, the convex portion being convex in a top surface direction of the substrate.

Abstract: A droplet measurement method is described. The droplet measurement method may include discharging a droplet on a substrate, scanning the droplet by moving a scanning unit, and calculating a volume of the droplet by using the thicknesses of the portions of the droplet. The scanning unit may include optical scanners arranged in multiple directions, storing thicknesses of portions of the droplet scanned by the scanning unit.

Abstract: A color conversion layer and a manufacturing method of the same are provided. The manufacturing method of the color conversion layer includes steps of: subjecting a block copolymer thin film to self-assembly to obtain a self-assembled block copolymer thin film, including a plurality of main parts arranged in order, and a plurality of spacing parts disposed between the plurality of main parts; forming a protective layer covering the main parts; removing the spacing parts to form a plurality of grooves arranged in order; and dropping a color conversion layer ink into the grooves, followed by drying the color conversion layer ink to obtain the color conversion layer.

Abstract: A display device includes a TFT substrate including a flattening layer on a surface, a sealing film including a resin film that is an ink-jet resin film, and a first bank that surrounds the flattening layer, is covered with the resin film on an inner side, and has a frame shape. The flattening layer includes, on an entire periphery of a circumferential end portion thereof, a recessed and protruding portion provided with recesses and protrusions having sizes different on a first side and a second side in a plan view.

Abstract: The light-emitting device includes: a base substrate; a light-emitting unit, disposed on the base substrate; and a thin film packaging structure disposed on a side, distal from the base substrate, of the light-emitting unit, wherein the thin film packaging structure includes a target packaging film layer of at least one packaging film layer is provided with a first packaging portion and a second packaging portion which are arranged in the same layer and are in contact with each other, an orthographic projection of the first packaging portion on the base substrate at least partially overlaps an orthographic projection of the light-emitting unit on the base substrate, an orthographic projection of the second packaging portion on the base substrate at least partially overlaps the orthographic projection of the light-emitting unit, and a refractive index of the first packaging portion is less than a refractive index of the second packaging portion.

Abstract: A display substrate, a method for manufacturing the same and a display device are provided. The display substrate includes a base, a pixel definition layer disposed on the base, and a light-emitting unit disposed in a pixel opening region defined by the pixel definition layer; the display substrate further includes: a diversion channel provided on a surface of the pixel definition layer that is away from the base; and an encapsulation layer covering the light-emitting unit and the pixel definition layer, wherein the encapsulation layer fills the diversion channel. The display substrate in the present disclosure is used for displaying an image.

Abstract: Provided is a display substrate having a polygonal encapsulation region with a plurality of edges and a periphery region surrounding the encapsulation region. The display substrate includes a base substrate, and a partition structure within the periphery region on a side of the base substrate. The partition structure includes a plurality of isolation dams, arranged at intervals along a direction away from the encapsulation region, outside each edge of the encapsulation region. The plurality of edges include a first edge and a second edge, and a plurality of first isolation dams outside the first edge are not in connection with, and have more dams than, a plurality of second isolation dams outside the second edge.

Abstract: Integrated circuit packages and methods of forming the same are disclosed. A first die is mounted on a first side of a workpiece, the workpiece including a second die. The workpiece is mounted to a front side of a package substrate, where the first die is at least partially disposed in a through hole in the package substrate. A heat dissipation feature may be attached on a second side of the workpiece. An encapsulant may be formed on the front side of the package substrate around the workpiece.

Abstract: A method of fabricating a display substrate having a display area and a peripheral area is provided. The method includes forming a plurality of light emitting elements on a base substrate and in the display area; forming an encapsulating layer on a side of the plurality of light emitting elements distal to the base substrate to encapsulate the plurality of light emitting elements; forming an insulating layer, wherein the insulating layer is formed between the encapsulating layer and the base substrate; and forming a first barrier wall in the peripheral area and on a side of the insulating layer away from the base substrate, the first barrier wall forming a first enclosure substantially surrounding a first area. A side of the first barrier wall away from the base substrate is wider than a side of the first barrier wall closer to the base substrate.

Abstract: According to one aspect, a method of fabricating a semiconductor structure includes cutting a semiconductor fin extending along a substrate. Cutting the semiconductor fin can comprise forming a fin cut mask. The fin cut mask can define a number of masked regions and a number of cut regions. The method can include cutting the fin into a number of fin parts by etching the fin in the cut regions. The method can further comprise forming an epitaxial semiconductor capping layer on the fin prior to forming the fin cut mask or on the fin parts subsequent to cutting the fin. A capping layer material and a fin material can be lattice mismatched. According to another aspect, a corresponding semiconductor structure comprises fin parts.

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.

Abstract: Integrated circuits with stacked transistors and methods of manufacturing the same are disclosed. An example integrated circuit includes a first transistor in a first portion of the integrated circuit, and a second transistor stacked above the first transistor and in a second portion of the integrated circuit above the first portion. The integrated circuit further includes a bonding layer between the first and second vertical portions of the integrated circuit. The bonding layer includes an opening extending therethrough between the first and second vertical portions of the integrated circuit. The integrated circuit also includes a gate dielectric on an inner wall of the opening.