Abstract: Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.

Abstract: An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.

Abstract: An input/output (I/O) cell including one or more driver-capable segments and one or more on-die termination (ODT) capable segments. The I/O cell may be configured as an output driver in a first mode and Thevenin equivalent termination in a second mode.

Abstract: Methods for differential pair conductor routing in a logic circuit. One embodiment includes a method for differential pair conductor routing in a logic circuit, by routing conductors of a first line width to obtain a first routing for a first logic library, wherein vertical and horizontal paths are separated such that vertical and horizontal conductors do not short, wherein connections between the vertical and horizontal paths are provided by vias, separating conductor paths in the first routing into differential paths by splitting the conductors of a first line width into spaced parallel conductors of a second line width, where the second line width is smaller than the first line width, separating the vias into pairs of vias, and replacing the first logic library with a differential logic library.

Abstract: An impedance code generation circuit includes an impedance unit configured to drive a calibration node to a first level by using an impedance value determined by an impedance code, a code generation unit configured to generate the impedance code so that a voltage of the calibration node has a voltage level between a first reference voltage and a second reference voltage, and a reference voltage generation unit configured to generate the first reference voltage and the second reference voltage in response to the impedance code.

Abstract: A programmable logic device (PLD) is disclosed that includes a non-volatile memory; a shadow register; and a data shift register (DSR) configurable to receive control information from an external programming tool, wherein the DSR is configured to shift the control information into the shadow register if the PLD is in a first programming mode, the PLD being configurable to operate in the first programming mode using the control information stored in the shadow register without the control information being stored in the non-volatile memory.

Abstract: Techniques are provided to reduce glitches at an output signal node when a device is switched to and from a low power operation mode. In one example, a method of operating a device includes providing power to operate a signal source of the device during a normal operation mode of the device. The method also includes passing an output signal from the signal source through a signal path to an output node during the normal operation mode. The method also includes receiving an operation mode signal to switch the device from the normal operation mode to a low power operation mode. The method also includes disabling the signal path to prevent glitches from appearing at the output node during the switch from the normal operation mode to the low power operation mode. The method also includes continuing providing power to the signal source until after the signal path is disabled.

Abstract: A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

Abstract: A capacitive full-wave circuit for LED light strings makes use of capacitors and diodes together to drive a LED string with full AC waves. Different from the conventional four-diode full-wave rectifying circuit, one embodiment of capacitive full-wave circuit includes two capacitors and two diodes. Because of the large imaginary impedance, the capacitors not only limit and the voltage and current through the LEDs, but also consume almost no electrical power. The electrical current-voltage performance can be further improved by introducing four resistors with a cost of some additional power consumption. A LED light string module with the capacitive full-wave circuit is also presented, with the capacitive full-wave circuit integrated inside of a front power plug and a back power socket.

Abstract: A power conversion driving circuit is provided. The power conversion drive circuit includes a converting circuit, a control circuit and a load circuit. The converting circuit is coupled to an input voltage. The control circuit is coupled to the converting circuit for controlling the converting circuit to convert the input voltage to an output voltage. The load circuit includes a load detecting unit and a load. The load is coupled to the output voltage, and the load detecting unit is coupled to a detecting voltage source. The load detecting unit generates a load detecting signal to re-start the control circuit when the load circuit is inserted into the power conversion driving circuit.

Abstract: A lighting control system employs a microcontroller to generate time-delay pulses that are synchronized with the AC power. The time-delay pulses control conduction period of a semi-conductor switching device for transmitting AC power to a lighting load. This lighting control system enables the lighting load performing two-level or multi-level illumination in a simple and power saving manner. While the conventional circuits use cumbersome passive resistor-capacitor scheme to generate required timing control, this lighting control system uses simple scheme based on a built-in oscillator in the microcontroller. This scheme provides high flexibility and accuracy to implement delay-time triggering. The system and method in the present invention may simultaneously be applicable to lighting loads of different impedance types, especially to incandescent lamp, fluorescent lamp, and AC light emitting diode.

Abstract: A lighting system includes a first and a second controllable light sources generating, respectively, a first and a second lights; a first detector configured to receive at least a portion of the first light and measure at least one attribute thereof in a first predetermined location proximate to the first controllable light source; a memory configured to store at least one of a specification of the second controllable light source and at least one operating parameter of the first controllable light source. The system also includes a processor configured to receive the at least one attribute of the first light, and to control the second controllable light source to generate the second light having an attribute that substantially matches the attribute of the first light in a predetermined second location.

Abstract: Embodiments of the present invention provide for the rapid reignition of a high intensity discharge lamp. In one embodiment of the invention, an apparatus for a fast reigntion of a high intensity discharge lamp is disclosed. The apparatus is comprised of a ballast operatively coupled to the lamp that is configured to receive power from a power supply. The apparatus is also comprised of a timer circuit that enters a timing phase and produces a quantum of timing information when the lamp ceases receiving power from the power supply. This timer circuit does not require external power during the timing phase. The apparatus is additionally comprised of a control circuit that receives the timing information and permits the ballast to reignite the lamp based on the information.

Abstract: An integrated circuit enabling asynchronous data communication is disclosed. The integrated circuit comprises a plurality of circuit blocks, each circuit block of the plurality of circuit blocks comprising programmable resources; and a routing network coupled to each circuit block of the plurality of circuit blocks, the routing network enabling asynchronous data communication with the plurality of circuit blocks. Each circuit block of the plurality of circuit blocks synchronously processes data received from the routing network. A method of routing data in an integrated circuit is also disclosed.

Abstract: The present invention provides an configuration setting device of integrated circuit and the configuration setting method thereof, in which the configuration setting device comprises a signal receiving terminal, a voltage output unit coupled to the signal receiving terminal, and a detector coupled to the signal receiving terminal. The signal receiving terminal is used to receive the input signal at the outer of the integrated circuit, and the voltage output unit generated at the inner of the integrated circuit is used to output a voltage signal based on the enable signal, and the detector is used to detect a level at the signal receiving terminal to output a configuration signal; wherein, the signal level generated at the signal receiving terminal is determined by the input signal and the voltage signal.

Abstract: A high speed flip-flop circuit and a configuration method thereof are provided. A small number of transistors may be used to configure a flip-flop circuit, so that the flip-flop circuit may be operated at a high-speed. Additionally, an area occupied by the flip-flop circuit may be reduced, and power consumption may be reduced. Accordingly, the flip-flop circuit may be integrated together with a microwave frequency integrated circuit using a Gallium Arsenide (GaAs) compound semiconductor process.

Abstract: A repair circuit having a repair controller which is capable of reducing unnecessary current dissipation by interrupting a control operation to redundant cells that are unused for replacement of defective cells is presented. The repair circuit includes a repair controller and a repair signal generator. The repair controller is configured to generate a first drive voltage, a second drive voltage and a repair control signal depending on whether or not a defective cell exists. The repair signal generator driven by the first and second drive voltages in which the repair signal generator is configured to generate a repair signal, for repairing the defective cell, in response to receiving the repair control signal and an external address.

Abstract: One aspect provides an input/output cell. The input/output cell, in one example, includes an input/output layout boundary delineated on a substrate, wherein the input/output layout boundary defines a first side parallel and opposing a second side, a third side parallel and opposing a fourth side, wherein the first and second sides are substantially perpendicular the third and fourth sides. The input/output cell, in this example, further includes input/output transistors positioned within the input/output layout boundary over the substrate. The input/output cell, in this example, further includes first and second power conductors and first and second ground conductors located over the substrate, the first power conductor and first ground conductor extending entirely between the first and second sides and the second power conductor and second ground conductor extending entirely between the third and fourth sides.

Abstract: The present invention of a reverse polarity series type LED is formed by two sets of LED and diode assemblies in reverse polarity series connection wherein the first set is consisted of at least one or multiple homopolar series or parallel connected or series and parallel connected LEDs, and the second set consisting of at least one or more homopolar parallel or series connected or series and parallel connected LEDs for further connection to the drive circuit formed by current-limiting impedance and/or power storage and discharging devices and/or voltage-limit circuit devices in order to produce the required operational characteristics.

Abstract: An apparatus which provides a self-reconfigurable analog resonant computer employing a fixed electronic circuit schematic which performs computing logic operations (for example OR, AND, NOR, and XOR Boolean logic) without physical re-wiring and whose components only include passive circuit elements such as resistors, capacitors, inductors, and memristor devices. The computational logic self-reconfiguration process in the circuit takes place as training input signals, which are input causing the impedance state of the memristor device to change. Once the training process is completed, the circuit is probed to determine whether the desired logic operation has been programmed.