Abstract: A physically unclonable function (PUF) device, with corresponding method, is provided for characterizing an integrated circuit. The PUF device includes a digital clock manager (DCM), a Butterfly circuit incorporated within the integrated circuit, and a shift register. The DCM receives a clock input signal (CLK) and imposes a temporal offset to produce a phase-shift signal (PS). The Butterfly circuit receives a first excite signal as said CLK and a second excite signal as said PS. In response, the Butterfly circuit produces an output that shifts state in response to a non-concurrent change in the CLK and PS. The shift register increments a shift count in response to the output.

Abstract: A plasma source for a substrate is provided. The plasma source may include a source electrode and an impedance box. The source electrode receives a source Radio Frequency (RF) from the external and generates plasma based on capacitive coupling within a vacuum chamber. The impedance box connects at one end to an outer circumference surface of the source electrode, and is grounded at the other end to the vacuum chamber, and controls an electric current flowing from the source electrode to the vacuum chamber by the source RF.

Abstract: A lighting system for an emergency exit from an occupied space: an array of lighting elements located around the emergency exit to illuminate the exit and facilitate egress for an occupant of the space; a control unit; and sensors to detect one or more trigger conditions and actuate the lighting elements in response to a first trigger condition from any of the sensors, the sensors comprising: an impulse detector operable to send a signal to the control unit indicating that the impulse detector has experienced an impulse; and a roll and/or pitch detector operable to send a signal to the control unit indicating that the roll and/or pitch detector has experienced roll and/or pitch, wherein upon detection of the first trigger condition the control unit actuates one or more of the lighting elements to illuminate the exit.

Abstract: The disclosed embodiments provide a first-in, first-out (FIFO) circuit that operates asynchronously. The FIFO circuit includes a data path that contains data latches sequentially connected through data-wire segments. The FIFO circuit also includes a control circuit that generates control signals for the data latches so that the data path behaves like a FIFO. The control circuit includes control components sequentially connected to each other through control-wire segments and repeaters located within the control-wire segments. The control components are configured to asynchronously generate the control signals for the data latches, and the repeaters are configured to repeat asynchronous signals communicated between the asynchronous control components.

Abstract: Embodiments of an integrated circuit driver, a method for operating integrated circuit driver, and predrivers are described. In one embodiment of the integrated circuit driver, a bias control circuit provides a bias signal for a first mode and a second mode. The bias signal has a first voltage level associated with operation in the first mode and a second voltage level associated with operation in the second mode. An output driver circuit receives the bias signal. In the first mode, the output driver circuit operates as a supply referenced driver, and in the second mode, the output driver circuit operates as a ground referenced driver.

Abstract: One interface chip and a plurality of core chips are electrically connected via a plurality of through silicon vias. A data signal of a driver circuit is input into the core chip via any one of the through silicon vias. An output switching circuit activates any one of tri-state inverters and selects one of the through silicon vias. The tri-state inverters amplify the data signal and transmit it to the through silicon via. Similarly, an input switching circuit activates any one of tri-state inverters. These tri-state inverters also amplify the data signal transmitted from the through silicon via and supply it to the receiver circuit.

Abstract: Systems, methods, and apparatus, including computer program products, for providing termination resistance in a memory module are provided. An apparatus is provided that includes a plurality of memory circuits; an interface circuit operable to communicate with the plurality of memory circuits and to communicate with a memory controller; and a transmission line electrically coupling the interface circuit to a memory controller, wherein the interface circuit is operable to terminate the transmission line with a single termination resistance that is selected based on a plurality of resistance-setting commands received from the memory controller.

Abstract: Memory for a semiconductor device is disclosed. The memory array comprises: a memory cell replicated in rows and columns to form an array; and a plurality of first horizontal decode signals, each horizontal signal common to all the memory cells in a said row; and a plurality of first vertical decode signals, each vertical signal common to all the memory cells in a said column; wherein, said replicated memory cell further comprises: a storage device to store data; and a first decode device to receive a said first horizontal decode signal and a said first vertical decode signal and generate a first local decode signal to access a first unique memory cell in the array.

Abstract: Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

Abstract: Methods and a system for continuous integrity checking of configuration data of programmable device are disclosed. In one embodiment, a method includes performing a redundancy check (RC) of configuration data loaded to configuration registers to produce a master RC data. The method further includes iteratively comparing a current RC data obtained by performing the redundancy check (RC) of current configuration data of the configuration registers with the master RC data until there is a mismatch between the current RC data and the master RC data. Additionally, the method includes performing an exception event in response to the mismatch.

Abstract: A light emitting diode driving apparatus 10 of the present invention includes: a driving voltage generating section 11 for generating a driving voltage Vout of an LED; a driving current control section 12 for PWM controlling driving currents iW1 to iW3 that flow through the LED; and a monitor voltage generating section 13 that monitors the driving voltage Vout, and that generates a monitor voltage Vm during an OFF period of the driving current by superposing on a predetermined reference voltage Vref, which is used as a standard, a voltage corresponding to a difference occurring in the driving voltage Vout during the OFF period.

Abstract: A transmission apparatus for differential communication includes a driver bridge circuit and a pair of noise protection circuits. The driver bridge circuit includes four output devices that are independently connected between each of a pair of transmission lines and a power line or a ground line. Each noise protection circuit is provided to a corresponding transmission lines. Each noise protection circuit includes a ground potential detector and an impedance controller. The ground potential detector detects a potential of the corresponding transmission line with respect to the ground line. The impedance controller causes an impedance of the corresponding transmission line with respect to the ground line to become equal to an impedance of the other transmission line with respect to the ground line, when the detected potential becomes outside a predetermined potential range.

Abstract: The present invention is directed to reduce the chip area of a semiconductor integrated circuit. A semiconductor integrated circuit of the invention includes a first transistor, a second transistor disposed adjacent to the first transistor along a Y axis, and a third transistor disposed adjacent to the second transistor along an X axis. The semiconductor integrated circuit further includes a fourth transistor disposed adjacent to the third transistor along the Y axis and disposed adjacent to the first transistor along the X axis. The first to fourth transistors share a well, and an output signal of the first transistor and an output signal of the second transistor have phases opposite to each other. An output signal of the second transistor and an output signal of the third transistor have phases opposite to each other. An output of the third transistor and an output signal of the fourth transistor have phases opposite to each other.

Abstract: Various types of memory circuits are described. A memory circuit may include a state-storage feedback loop coupled to a clock input and to a data input. The data input is introduced into the feedback loop at multiple points, and propagated in parallel from those points to other points in the feedback loop.

Abstract: A delay line compensated for process, voltage, and temperature variations, includes a delay locked loop (DLL) configured to delay a digital signal by the clock period of the digital signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to a digital control signal. A fractionating circuit is configured to generate a digital delay line control signal that is a fraction of the digital control signal. A digital delay line is arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delay quanta in response to the digital delay line control signal.

Abstract: A multiple supply voltage device includes an input/output (I/O) network operative at a first supply voltage, a core network coupled to the I/O network and operative at a second supply voltage, and a power-on-control (POC) network coupled to the I/O network and the core network. The POC network is configured to transmit a POC signal to the I/O network and includes an adjustable current power up/down detector configured to detect a power state of the core network. The POC network also includes processing circuitry coupled to the adjustable current power up/down detector and configured to process the power state into the POC signal, and one or more feedback circuits. For reducing the leakage current while also improving the power-up/down detection speed, the feedback circuit(s) are coupled to the adjustable current power up/down detector and configured to provide feedback signals to adjust a current capacity of the adjustable current power up/down detector.

Abstract: A quantum processor may employ a heterogeneous qubit-coupling architecture to reduce the average number of intermediate coupling steps that separate any two qubits in the quantum processor, while limiting the overall susceptibility to noise of the qubits. The architecture may effectively realize a small-world network where the average qubit has a low connectivity (thereby allowing it to operate substantially quantum mechanically) but each qubit is within a relatively low number of intermediate coupling steps from any other qubit. To realize such, some of the qubits may have a relatively high connectivity, and may thus operate substantially classically.

Abstract: An interface device includes a differential signal transmitter, a differential signal receiver, a first coupling capacitor, a second coupling capacitor, a direct current (DC) signal transmitter, and a DC signal receiver. The differential signal transmitter transmits a differential signal to the differential signal receiver via a differential signal line including a first signal line and a second signal line. The first coupling capacitor is communicatively coupled to the first signal line and to the differential signal transmitter. The second coupling capacitor is communicatively coupled to the first signal line and to the differential signal receiver. The DC signal transmitter transmits a DC signal via the first signal line. The DC signal receiver receives the DC signal via the first signal line.

Abstract: A two-wire load control device, such as a dimmer, is operable to control the amount of power delivered to an electrical load, such as a magnetic low-voltage (MLV) load, and comprises a bidirectional semiconductor switch, a timing circuit, a trigger circuit having a variable voltage threshold, and a clamp circuit. When a timing voltage signal of the timing circuit exceeds an initial magnitude of the variable voltage threshold, the trigger circuit is operable to render the semiconductor switch conductive, reduce the timing voltage signal to a predetermined magnitude less than the initial magnitude, and to increase the variable voltage threshold to a second magnitude greater than the first magnitude. The clamp circuit limits the magnitude of the timing voltage signal to a clamp magnitude between the initial magnitude and the second magnitude, thereby preventing the timing voltage signal from exceeding the second magnitude.

Abstract: The detector is reduced in DC power consumption when an input signal is at a low amplitude level. The detector includes first and second input terminals, first and second transistors, and a load element. The first and second input terminals are supplied with complementary input signals reverse to each other in phase. The first input terminal is connected to the first input electrode of the first transistor and the second input electrode of the second transistor. The second input terminal is connected to the second input electrode of the first transistor and the first input electrode of the second transistor. The load element is connected between output electrodes of the transistors and an operating voltage point. A detection voltage resulting from full-wave rectification arises from a circuit node. In the condition where a signal input to the input terminals is at a low amplitude level, the transistors are both in OFF state. Thus, DC power consumption is reduced.