Abstract: A configurable integrated circuit (“IC”) that includes several configurable tiles, each of which has a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits. The configurable IC provides a set of associated configurable logic circuits for performing a particular portion of a larger arithmetic operation. The configurable IC provides a carry circuit for generating a carry out signal for the particular portion of the larger arithmetic operation. A configurable storage element is for configurably storing the carry out signal and for providing the stored carry out signal to the carry circuit for performing a subsequent portion of the larger arithmetic operation. The configurable IC provides a configurable interconnect/storage element for configurably routing a carry signal from a first carry chain to a second carry chain and for storing the routed carry signal.

Abstract: A semiconductor device includes a first circuit block connected between first and second power lines, a logic circuit that receives an output signal of the first circuit block that is connected between the first power line and a fourth power line or a third power line and the second power line, and a second circuit block that receives an output signal of the logic circuit that is connected between the third and fourth power lines. In an active state, a first potential is supplied and in a standby state, a second potential lower than the first potential is supplied between the first and second power lines. In any of the active state and the standby state, the first potential is supplied between the third and fourth power lines. With this configuration, speeding-up of a critical path can be realized while maintaining a subthreshold current low.

Abstract: Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.

Abstract: A personal digital assistant includes a body, and a touch panel. The body includes a display screen. The touch panel is located on a surface of the display screen. The touch panel includes at least one transparent conductive layer including a carbon nanotube layer.

Abstract: A systems and methods for providing phase lock conditions detection, such as a quality of phase lock and loss of lock detection, are described herein. One exemplary method comprises detecting an output frequency, comparing the output frequency with a first reference signal, providing a first signal and a second signal as a function of the output frequency and first reference signal comparison, receiving a predetermined threshold from a second reference signal, monitoring a deviation of the first and second signals from the predetermined threshold, generating a third signal as a function of the deviation, comparing the third signal to a window threshold wherein the window threshold is set based on a predetermined loop variable, generating a fourth signal a function of the third signal and the window threshold comparison, and providing an alarm based on the fourth signal.

Abstract: Techniques are described that can be used to determine a transmitter power level of a mobile station at cell edge. To determine transmitter power level, the technique considers at least a balance of power transmitted by mobile stations near cell edge and power transmitted by mobile stations closer to cell center, target mean received power by the base station from mobile stations near center cell, target mean power transmitted from cell edge mobile stations, signal-to-interference-power ratio between signals transmitted from base stations of different cells to the mobile station at cell edge, and channel gain.

Abstract: A system and method for detecting soft-failures in integrated circuits is provided. A circuit includes a combinatorial logic block having a first signal input and a second signal input, and a latch coupled to an output of the combinatorial logic block. The combinatorial logic block produces a pulse when only one of either a first signal provided by the first signal input or a second signal provided by the second signal input is a logical high value, and the latch captures the pulse if the pulse has a pulse width greater than a second threshold. The pulse has a pulse width that is based on a timing difference between a first signal transition on the first signal and a second signal transition on the second signal, the combinatorial logic block produces the pulse if the timing difference is greater than a first threshold, and the combinatorial logic block operates with balanced inputs.

Abstract: A method for testing a line including an input/output pin of a programmable logic circuit, said line including at least one individual line extending from the input/output pin to a peripheral element, said input/output pin being able to be either at a high logic level or at a low logic level opposite to the high logic level. The method includes, between an initial driving instant and a final driving instant, a step for driving the input/output pin in which a driving voltage is applied to the terminals of the input/output pin.

Abstract: A method is disclosed for controlling an output impedance of an electronic device of the type having an impedance control terminal to which an external load is to be connected such that a predetermined value of the voltage at the impedance control terminal controls the output impedance of the device. The method is comprised of comparing a reference voltage to a voltage at the impedance control terminal. A variable count signal representing a count value is produced in response to the comparing. The impedance of a variable impedance circuit is varied in response to the count signal, wherein the impedance of the variable impedance circuit controls the voltage at the impedance control terminal. A device connected in parallel with the variable impedance circuit is periodically operated to change (increase/decrease) the impedance of the variable impedance circuit. An apparatus for performing the method is also disclosed.

Abstract: Some embodiments show a storage circuit with fault detection. The storage circuit comprises, first and second fault detection circuits each comprising a first stable state and a second stable state, wherein each of the first and the second fault detection circuits is configured such that a fault signal strength necessary to cause switching from the first stable state to the second stable state is different from a fault signal strength necessary to cause switching from the second stable state to the first stable state.

Abstract: Example driver circuits can utilize shared-charge recycling charge pump structures. In particular, an example shared-charge recycling process may be applied to a clock buffer and charge transfer cells of the charge pump in a driver circuit. An example recycling process may include recycling of shared charges between the capacitors/capacitances in the charge transfer cells. An example recycling process may use the charges in one or more capacitors to charge one or more other capacitors before the charges are wasted or otherwise discharged to ground. Such recycling may significantly reduce the power consumption of the charge pump while still providing a high output voltage level, according to an example embodiment of the invention.

Abstract: A controller for use in a light emitting diode (LED) driver is disclosed. An example controller includes an input circuit coupled to receive an ac input signal from an ac source. A dimmer disabler circuit is included and is coupled to be responsive to the input circuit to detect an absence of a portion of an ac half cycle the ac input signal for one or more consecutive ac half cycles from the ac input signal. A regulator circuit is included and is coupled to control a switching of a switch to regulate a transfer of energy from the ac input signal to a LED load to be coupled to an output of the LED driver. The dimmer disabler circuit is coupled to disable the regulator circuit from switching the switch in response to the detection of the absence of the portion of the ac half cycle from the ac input signal for the one or more consecutive ac half cycles from the ac input signal.

Abstract: An impedance calibration mode control circuit includes: a first signal generating unit configured to generate a first calibration control signal in response to a ZQ calibration command received after a power-up operation; and a second signal generating unit configured to generate a second calibration control signal during a refresh operation of a semiconductor device.

Abstract: A level shifter converts an input signal having an amplitude between a ground and a first power supply voltage into an output signal having an amplitude between the ground and a second power supply voltage. The level shifter includes an input unit, driven by the first power supply voltage, that raises a first pulse signal at a rise of the input signal and raises a second pulse signal having the same polarity as the first pulse signal at a fall of the input signal, and a level shift unit that converts a signal level of the first pulse signal into an amplitude level of the second power supply voltage, and converts a signal level of the second pulse signal into an amplitude level of the second power supply voltage.

Abstract: A circuit arrangement and method utilize a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers.

Abstract: Disclosed is a novel circuit able to generate any logic combination possible as a function of the input logic signals. The circuit is described as a 2 input logistic map circuit but may be expanded to 3 or more inputs as required. Further disclosed is a universal logic array with variable circuit topology. A metallization layer and/or a via interconnection between cells in the array elements produce a circuit topology that implements a Boolean function and/or chaotic function and/or a logic function. The novel circuit provides a circuit topology for secure applications with no obvious physical correspondence between control signal values and input to output mapping. Further disclosed is a network which has a power signature independent of input signal state and output transition. This provides a very useful circuit to protect data from decryption from power signature analysis in secure applications.

Abstract: A starting circuit arrangement in which a gas discharge lamp is assigned a supply circuit having at least one inductor arranged in series with the gas discharge lamp, wherein the starting circuit arrangement comprises a starting transformer connected on the primary side to a starting triggering circuit and connected on the secondary side to the lamp for the transmission of a starting pulse, an input energy source for the starting triggering circuit, a first switch means in the starting triggering circuit, an electronic control device which drives the first switch means. The starting circuit arrangement has, on the supply side, an input terminal connected in the supply circuit of the lamp between the inductor and the lamp, and a means provided for reproducing the phase profile of an AC supply variable of the lamp after starting of the lamp.

Abstract: A semiconductor device includes a first transistor included in a latch circuit, a second transistor that is included in the latch circuit and is formed in a well in which the first transistor is formed, the second transistor having a conduction type identical to that of the first transistor, and a well contact that is provided between the first transistor and the second transistor and connects a power supply to the well.

Abstract: A countermeasure in a logic circuit having a logic gate supplying a binary output signal, the method including supplying binary data having random values to inputs of logic circuit during a precharge phase; supplying data to process to inputs of the logic circuit during a data processing phase; supplying on input of the logic circuit a precharge command signal launching a precharge phase; and under the effect of the precharge command signal, adapting the functioning of a logic gate of the logic circuit, statistically unbalanced, so that the output signal of the logic gate is in a binary state with a same probability as the random binary data supplied on input of the logic circuit during the precharge phase.

Abstract: The disclosure relates to an AC LED dimmer and dimming method thereof. The AC LED dimmer includes a rectifier receiving AC voltage from an AC voltage source and full-wave rectifying the AC voltage; a direct current (DC)/DC converter receiving the full-wave rectified voltage from the rectifier, generating a full-wave rectified stepped-up voltage, and generating a pulse enable signal; a pulse width modulation controller receiving the full-wave rectified stepped-up voltage and generating a pulse width modulation signal to dim an AC LED in response to the pulse enable signal; a switch driving the AC LED under control of the pulse width modulation signal, and an electromagnetic interference (EMI) filter to be connected between the AC voltage source and the switch to eliminate electromagnetic interference from the AC voltage source. Accordingly, the dimmer can perform an efficient and linear dimming function and suppress harmonics.