Abstract: A processor for building a homogeneous dual computing system is shown. The processor has a trusted core, a normal core, and a shared cache. The trusted core has an access right to an isolated storage space of a system memory. The normal core is homogeneous with the trusted core, and is prohibited from accessing the isolated storage space. In response to a cache flush instruction issued by the normal core, the trusted core initiates and executes a second cache write-back instruction that is different from the first cache write-back instruction. According to the second cache write-back instruction, isolated data associated with the isolated storage space and cached in the shared cache is written back to the isolated storage space before being flushed.

Abstract: A storage device includes at least one nonvolatile memory device and a storage controller. The storage controller controls the at least one nonvolatile memory device based on a request from an external host. The storage controller adaptively adjusts an impedance of a transmission driver based on a change of an operating temperature of the storage device. The transmission driver transmits a transmission signal to the external host through a link. The storage device may increase an eye height of the transmission signal transmitted to the host through the link by decreasing impedance of the transmission driver as the operating temperature increases. Therefore, the storage device according to example embodiments may maintain reliability of the link even though the operating temperature of the storage device increases.

Abstract: Methods, systems, and devices for atomic write operations are described. A host system may receive a sequence of data that includes a first set of data and a second set of data. The host system may determine, based on the sequence of data, a first set of contiguous logical addresses for the first set of data and a second set of contiguous logical address for the second set of data. The host system may then transmit to a memory system a write command that indicates the first set of contiguous logical addresses and the second set of contiguous logical addresses. The first set of contiguous logical addresses may be discontiguous with the second set of contiguous logical addresses.

Abstract: A cache may include multiple request handling pipes, each of which may further include multiple request buffers, for storing device requests from one or more processors to one or more devices. Some of the device requests may require to be sent to the devices according to an order. For a given one of such device requests, the cache may select a request handling pipe, based on an address indicated by the device request, and select a request buffer, based on the available entries of the request buffers of the selected request handling pipe, to store the device request. The cache may further use a first-level and a second-level token stores to track and maintain the device requests in order when transmitting the device requests to the devices.

Abstract: Apparatuses and methods related to providing coherent memory access. An apparatus for providing coherent memory access can include a memory array, a first processing resource, a first cache line and a second cache line coupled to the memory array, a first cache controller, and a second cache controller. The first cache controller coupled to the first processing resource and to the first cache line can be configured to provide coherent access to data stored in the second cache line and corresponding to a memory address. A second cache controller coupled through an interface to a second processing resource external to the apparatus and coupled to the second cache line can be configured to provide coherent access to the data stored in the first cache line and corresponding to the memory address.

Abstract: An apparatus can include control circuitry, a non-volatile memory device, and a volatile memory device. The control circuitry can be configured to receive a command presented according to a compute express link (CXL) protocol. The control circuitry can be further configured to cause data to be written to the non-volatile memory device or the volatile memory device, or both, in response to receipt of the command while refraining from writing the data to a cache that is external to the apparatus.

Abstract: In an example, there is disclosed a host-fabric interface (HFI), including: an interconnect interface to communicatively couple the HFI to an interconnect; a network interface to communicatively couple the HFI to a network; network interface logic to provide communication between the interconnect and the network; a coprocessor configured to provide an offloaded function for the network; a memory; and a caching agent configured to: designate a region of the memory as a shared memory between the HFI and a core communicatively coupled to the HFI via the interconnect; receive a memory operation directed to the shared memory; and issue a memory instruction to the memory according to the memory operation.

Abstract: Methods that may be performed by a universal flash storage (UFS) system of a computing device for updating logical-to-physical (L2P) address mapping tables. Various embodiments may include enabling a device control mode (DCM) of host performance booster (HPB) based on a flush of a writebooster buffer to a normal storage of a UFS device of the UFS system, and updating an L2P address mapping table at a host device of the UFS system while DCM is enabled based on the flush of the writebooster buffer to the normal storage. Some embodiments may include generating a signal having an indicator of a UFS protocol information unit configured to indicate a change in an HPB mode at the UFS device based on the flush of the writebooster buffer to the normal storage, and sending the signal from the UFS device to the host device.

Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

Abstract: In some embodiments, an operating method of a storage device includes obtaining a plurality of points by searching for a first valley point between threshold voltage distributions of selection memory cells coupled to a selection word line of a plurality of word lines; calculating, using a first function, a first voltage level that corresponds to a first reference count value; calculating, using a second function, a second voltage level that corresponds to the first reference count value; classifying the selection memory cells into a plurality of coupling patterns according to an aggressor cell group of each of adjacent memory cells coupled to at least one adjacent word line adjacent to the selection word line; and performing a read operation, based on the plurality of coupling patterns of the selection memory cells, the first voltage level, and the second voltage level.

Abstract: Preventing applications from overconsuming shared storage resources, including: identifying one or more sub-regions of data stored on a storage device that are associated with an application of a known application type; compiling information describing the application's utilization of a storage system; determining that a storage system objective has not been met; and initiating, based on the information describing the application's utilization of the storage system, remediation actions.

Abstract: A data reduction device, a data reduction method, and a system including the data reduction device are provided. The data reduction device includes a control module configured to generate a control signal in response to a first kernel request received from an external entity, a direct memory access (DMA) engine configured to read request data corresponding to the first kernel request from an external entity in response to the control signal, and a data reduction core configured in such a manner that the request data is reduced through a first operation to be generated first reduction data or the first reduction data is reduced through a second operation to be generated as second reduction data.

Abstract: Methods, systems, and devices for cache block budgeting techniques are described. In some memory systems, a controller may configure a memory device with a cache. The cache may include a first subset of blocks configured to statically operate in a first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and a second mode. A block operating in the second mode may be configured to store relatively more bits per memory cell than a block operating in the first mode. The controller may track and store, for each block of the second subset of blocks, a respective ratio of cycles performed in the first mode to cycles performed in the second mode. The controller may select a block from the second subset of blocks to switch between modes responsive to a trigger and based on the respective ratio for the block.

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received.

Abstract: Disclosed herein is a device and method for dynamically processing of a command within a storage system. This includes identifying a plurality of non-volatile memory storage locations of the storage system that have at least one operation parameter associated with the plurality of non-volatile memory storage locations. For each identified plurality of non-volatile memory storage locations, there is a determination whether a value of the at least one operation parameter exceeds a predetermined threshold value. That value is representative of operation effects of the storage system on a corresponding storage location of the identified plurality of non-volatile memory storage locations.

Abstract: A method for performing an address translation context switch includes initializing a computer processor to a first context by storing information identifying the first context in a control register of the computer processor. The first context specifies a mapping of virtual addresses of instructions to physical memory addresses in a first memory area. Information identifying a second context is stored in a memory address translation independent storage, where the second context specifies mapping of virtual addresses of instructions to physical memory addresses in a second memory area. The information identifying the second context is written to the control register of the computer processor.

Abstract: Apparatus comprises address processing circuitry to detect information relating to an input memory address provided by address information tables; the address processing circuitry being configured to select an address information table at a given table level according to earlier information entry in an address information table; and the address processing circuitry being configured to select an information entry in the selected address information table according to an offset component, the offset component being defined so that contiguous instances of that portion of the input memory address indicate contiguously addressed information entries; the address processing circuitry comprising detector circuitry to detect whether indicator data is set to indicate whether a group of one or more contiguously addressed information entries in the selected address information table provide at least one base address indicating a location within a contiguously addressed region comprising multiple address information table

Abstract: Multiple transmit and receive channels in a communication transceiver may be dynamically configured using corresponding channel registers. The present disclosure proposes a profile-based direct memory access (PDMA) that can be used to transfer data from a memory and program specific profile registers in a randomly accessed addressing manner. PDMAs can offload the system processor from reprogramming many system registers based on external or internal events in a multi channels communication system. Furthermore, a PDMA based DMA controller is proposed to configure the frequency hopping registers of the transceiver based on PDMA.

Abstract: Embodiments are generally directed to cache structure and utilization. An embodiment of an apparatus includes one or more processors including a graphics processor; a memory for storage of data for processing by the one or more processors; and a cache to cache data from the memory; wherein the apparatus is to provide for dynamic overfetching of cache lines for the cache, including receiving a read request and accessing the cache for the requested data, and upon a miss in the cache, overfetching data from memory or a higher level cache in addition to fetching the requested data, wherein the overfetching of data is based at least in part on a current overfetch boundary, and provides for data is to be prefetched extending to the current overfetch boundary.

Abstract: A storage device includes a memory device that stores data, a storage controller that stores a data stream including plural frames in the memory device based on a write request from a host, and a scaler that generates a mapping table in which, for each frame, one or more logical addresses assigned to the frame is mapped to a frame number assigned to the frame. For each frame included in the data stream, the scaler performs an operation of obtaining the one or more logical addresses assigned to the frame by referring to the mapping table and providing a batch read request to the storage controller to read all the one or more logical addresses assigned to the frame. The storage controller controls the memory device to perform a read operation on a memory area corresponding to the one or more logical addresses based on the batch read request.