Abstract: A memory device is disclosed herein that leverages high ratio column MUXES to improve SEU resistance. The memory device may be utilized in an integrated circuit die and chip packages having the same. In one example, as semiconductor memory device is provided that includes first and second arrays of semiconductor memory cells, a plurality of sense amplifiers configured to read data states from the first and second arrays of memory cells, and a first plurality of high ratio MUXES connecting the first and second arrays of memory cells to the plurality of sense amplifiers.

Abstract: Recovery points can be used for replicating a virtual machine and reverting the virtual machine to a different state. A filter driver can monitor and capture input/output commands between a virtual machine and a virtual machine disk. The captured input/output commands can be used to create a recovery point. The recovery point can be associated with a bitmap that may be used to identify data blocks that have been modified between two versions of the virtual machine. Using this bitmap, a virtual machine may be reverted or restored to a different state by replacing modified data blocks and without replacing the entire virtual machine disk.

Abstract: An apparatus comprises a processing device configured to identify data to be migrated from a first device to a second device, the first device comprising a first storage stack supporting a first storage request block protocol. The processing device is also configured to determine whether a second storage stack of the second device supports the first storage request block protocol and, responsive to determining that the second storage stack of the second device does not support the first storage request block protocol, to convert storage request blocks directed to the data to be migrated from a first format of the first storage request block protocol to a second format of a second storage request block protocol. The processing device is further configured to migrate the data to the second device utilizing input-output operations comprising the storage request blocks in the second format of the second storage request block protocol.

Abstract: A system includes a memory device having a plurality of blocks. A first subset of the plurality of blocks is configured as single-level cell (SLC) memory and a second subset of the plurality of blocks is configured as multi-level cell (MLC) memory. A processing device, operatively coupled to the memory device, determines that a first block of a set of blocks of the first subset is a bad block. The processing device converts a second block of the set of blocks to the MLC memory of the second subset, wherein the second block is located in a neighboring plane of the memory device from that of the first block. The processing device converts a media endurance metric value of the second block from SLC-type to MLC-type.

Abstract: Provided is a method for managing an adaptive cache pool, which is performed by one or more processors, and includes receiving monitoring information on a cache memory divided into a plurality of cache pools, and adjusting a cache region associated with at least one of the plurality of cache pools based on the monitoring information.

Abstract: A data storage device with flash memory. The controller receives a mode selection command from a host. In response to the mode selection command, the controller sends a ready-to-transfer message to the host, to further receive a data out message from the host that is sent by the host in response to the ready-to-transfer message. The ready-to-transfer message and the data out message are UFS protocol information unit (UPIU) messages. The data out message is arranged to rewrite a first mode page setting among a plurality of mode page settings of firmware stored in the flash memory. In response to the data out message, the controller determines whether the data out message will change mode parameters which cannot be rewritten in the first mode page setting, to adopt or refuse new mode parameters issued through the data out message for the first mode page setting.

Abstract: A method for hot swapping a memory includes the following: in response to a triggering operation of a replacement key of an abnormal memory, data on the abnormal memory is copied to an idle memory when a system is powered on; and the abnormal memory is powered off and replaced with a new memory after the data is copied; and in response to the triggering operation of a power on key of the new memory, the new memory is powered on. A method for hot swapping a memory in the case where a system is not powered off is provided.

Abstract: An elastic memory system that may include memory banks, clients that are configured to obtain access requests associated with input addresses; first address converters that are configured to convert the input addresses to intermediate addresses within a linear address space; address scramblers that are configured to convert the intermediate addresses to physical addresses while balancing a load between the memory banks; atomic operation units; an interconnect that is configured to receive modified access requests that are associated with the physical addresses, and send the modified access requests downstream, wherein atomic modified access requests are sent to the atomic operation units; wherein the atomic operations units are configured to execute the atomic modified access requests; wherein the memory banks are configured to respond to the atomic modified access requests and to non-atomic modified access requests.

Abstract: A configuration file specifies a percentage value of data to validate. A synthetic full backup image of a source volume on cloud storage is accessed. The synthetic full backup is created by merging changed blocks of an incremental backup with another previous backup. A bitmap specifying locations of the changed blocks is examined. A region on the synthetic full backup beginning at a location corresponding to an initial changed block and ending at a location corresponding to a last changed block according to the bitmap is identified. The region is partitioned into a set of portions. Each portion is validated by randomly selecting blocks in a respective portion to validate. The validating of the respective portion continues until an amount of data validated in the respective portion reaches a size equal to the percentage value of a size of the incremental backup divided by a number of portions.

Abstract: USB Timer Boards and methods for backing up digital data from a host system onto storage devices which are automatically selected on an individual basis for digital connection, data exchange, data storage on a scheduled basis, and then digitally disconnected. When the storage devices are not selected and connected for backup data transfer and storage, the storage devices remain offline and not visible to the host system. USB Timer Boards and methods which backup data on one of a number of offline storage devices by connecting a selected storage device, backup data onto it and then disconnecting it, in order to isolate the backed-up data and optionally allow a different storage device to be used for the next back up event. The USB Timer Boards and methods include a real time clock and battery to allow the USB Timer Board to retain the exact date and time settings during power-off events.

Abstract: A first amount of energy to be stored at one or more power loss protection (PLP) components is determined to enable storage of data at a plurality of storage devices of a storage system upon an occurrence of a power failure. A first voltage is provided to the one or more PLP components that corresponds to the first amount of energy. A second amount of energy to be stored at the one or more PLP components is determined based on a change in the storage system. A second voltage is provided to the one or more PLP components that corresponds to the second amount of energy.

Abstract: A byte-addressable electronic device is provided. The electronic device includes a volatile memory device, a mapping table storing address information of the volatile memory device corresponding to address information of a non-volatile storage device, and information indicating whether a command related to data access is processed in relation to the address information of the volatile memory device, and a controller connected to a host processor, the volatile memory device, and the non-volatile storage device, and configured to process commands related to data access received from the host processor based on the mapping table.

Abstract: Multi-tile Memory Management for Detecting Cross Tile Access, Providing Multi-Tile Inference Scaling with multicasting of data via copy operation, and Providing Page Migration are disclosed herein. In one embodiment, a graphics processor for a multi-tile architecture includes a first graphics processing unit (GPU) having a memory and a memory controller, a second graphics processing unit (GPU) having a memory and a cross-GPU fabric to communicatively couple the first and second GPUs. The memory controller is configured to determine whether frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU in the multi-GPU configuration and to send a message to initiate a data transfer mechanism when frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU.

Abstract: A computing system (100) having a storage system that includes a storage device (130) and a host device (105), where the host device (105) is configured to issue memory access commands to the storage device (130). The computing system (100) further includes a prediction system (190) comprising processing circuitry that is configured to perform operations that cause the prediction system (190) to identify one or more components of the storage system (918) that limit random rad performance of the storage system (918). The operations further cause the prediction system (190) to obtain characterization data that is indicative of the impact of the one or more components on random read performance and generate a model based on the characterization data to predict random read performance of the storage system (918).

Abstract: An apparatus comprising translation circuitry to perform a translation operation to generate a translated second memory address within a second memory address space as a translation of a first memory address within a first memory address space, in which the translation circuitry is configured to generate the translated second memory address in dependence upon translation information stored at one or more translation information addresses; permission circuitry to perform an operation to detect permission information to indicate, for a given second memory address, whether memory access is permitted to the given second memory address; and access circuitry to allow access to data stored at the given second memory address when the permission information indicates that memory access is permitted to the given second memory address.

Abstract: A program method of a memory device having planes includes receiving a program command, obtaining an address associated with the program command, determining a first plane of the planes according to the address, and resetting a page register of the first plane without resetting one or more page registers of one or more remaining planes of the planes.

Abstract: A method of cache management includes: acquiring attributes of at least one file currently opened; extracting a first attribute subset related to a predetermined analysis target from among the attributes of the at least one file; determining region numbers of corresponding universal flash storage (UFS) device storage regions to be cached, based on the first attribute subset; and caching data of the corresponding UFS device storage regions to be cached into a cache memory, based on the region numbers.

Abstract: The present disclosure relates to a storage device and a storage system. The device comprises a storage, a storage controller, a control module, and a buffer module. The control module is configured to: when receiving a data read-write instruction, update the data read-write instruction by using a virtual address; apply for K buffer units in the buffer module; perform a write operation on the K buffer units by using data to be read and written; and when any of the K buffer units is full, directly start data transmission of the full buffer unit. By using the virtual storage address and by employing data block management, the present disclosure can update and forward an NVMe I/O command without applying for a storage space in advance, and can start data block transmission without checking the completion message.

Abstract: Systems, methods, and apparatus related to a memory system that manages an interface for a volatile memory device and a non-volatile memory device to control memory system power. In one approach, a controller evaluates a demand on memory performance. If the demand of a current computation task needed by the host is high, a DRAM device is powered-up to meet the demand. Otherwise, if the non-volatile memory device is adequate to meet the demand, the DRAM memory is partially or fully-powered down to save power. In another approach, a task performed for a host device uses one or more resources of a first memory device (e.g., DRAM). A performance capability of a second memory device (e.g., NVRAM) is determined. A controller of the memory system determines whether the performance capability of the second memory device is adequate to service the task.

Abstract: Reducing overheads of recording a replayable execution trace of a program's execution at a computer processor by omitting logging of accesses to memory addresses whose values can be reconstructed or predicted. A computer system determines that memory values corresponding to a range of memory addresses within a memory space for a process can be obtained separately from the process' execution, and configures a data structure for instructing a processor to omit logging of memory accesses when the processor accesses an address within this range while executing the process. Correspondingly, upon detecting a memory access while executing the process, the processor determines if it has been instructed to omit logging of the access by checking the data structure. When the data structure instructs the processor to omit logging of the access, the processor omits logging the memory access while it uses a cache to process the memory access.