Patents Examined by Shawn X. Gu
  • Patent number: 11068198
    Abstract: A data verification apparatus includes a storage, a management unit, and a verification unit. The storage includes a first storage and a second storage. The first storage stores first data and first status information. The second storage stores second data and second status information. The management unit controls a write process and updates the first status information and the second status information in response to the write process, the write process being a process of writing the first data to the first storage on a basis of data acquired by communication with an external apparatus, and thereafter writing the second data to the second storage on a basis of the data. The verification unit verifies, in a state in which the communication is disconnected, the first data and the second data on a basis of the first status information and the second status information.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: July 20, 2021
    Assignee: SUBARU CORPORATION
    Inventor: Yoshiaki Nakaso
  • Patent number: 11068171
    Abstract: A method, a computing device, and a non-transitory machine-readable medium for performing a multipath selection based on a determined quality of service for the paths. An example method includes a host computing device periodically polling a storage system for path information including an indication of a recommended storage controller. The host computing device periodically determines a quality of service information corresponding to a plurality of paths between the host computing device and a storage volume of the storage system, where at least one of the plurality of paths including the recommended storage controller. The host computing device identifies a fault corresponding to a path of the plurality of paths that routes I/O from the host computing device to the storage volume. The host computing device re-routes the I/O from the path to a different path of the plurality of paths, where the different path is selected for the re-routing based on the quality of service information and the path information.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: July 20, 2021
    Assignee: NETAPP, INC.
    Inventors: Joey Parnell, Steven Schremmer, Brandon Thompson, Mahmoud K. Jibbe
  • Patent number: 11068200
    Abstract: Methods and systems are provided for improving memory control. A memory architecture includes a plurality of memory units and an interface. A respective memory unit of the plurality of memory units is configured with a Processing-In-Memory (PIM) architecture. The interface includes a plurality of lines. The interface is coupled between the plurality of memory units and a host. The interface is configured to receive one or more signals from a host via the plurality of lines. The respective memory unit of the plurality of memory units is coupled with a respective line of the plurality of lines, and the respective memory unit is further configured to receive a respective signal of the one or more signals via the interface so as to be individually selected by the host.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: July 20, 2021
    Assignee: Alibaba Group Holding Limited
    Inventors: Dimin Niu, Lide Duan, Yuhao Wang, Xiaoxin Fan, Zhibin Xiao
  • Patent number: 11061593
    Abstract: A memory system includes a non-volatile memory device including at least one memory blocks storing a data and a controller coupled to the non-volatile memory device. The controller can perform at least one program operation or at least one erase operation within the at least one memory block. The controller can recognize an operation status of the at least one memory block in response to a time consumed for completing the at least one operation, and determine whether the at least one memory block is used and which priority is given to the at least one memory block based at least on the operation status so that the at least one memory block is allocated for a following operation.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 11055003
    Abstract: Apparatuses and methods can be related to supplementing AI processing in memory. An accelerator and/or a host can perform AI processing. Some of the operations comprising the AI processing can be performed by a memory device instead of by an accelerator and/or a host. The memory device can perform AI processing in conjunction with the host and/or accelerator to increase the efficiency of the host and/or accelerator.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Honglin Sun, Richard C. Murphy, Glen E. Hush
  • Patent number: 11055019
    Abstract: A memory controller configured to control a memory device including memory cells includes an input/output buffer configured to store input data provided from a host; a data converter configured to generate program data obtained by converting the input data such that the number of specific data patterns among data patterns to be stored in the memory cells is changed; and an operation controller configured to provide the program data to the memory device. The program data is generated by selectively inverting a plurality of pieces of logical page data included in the input data.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: July 6, 2021
    Assignee: SK hynix Inc.
    Inventor: Sang Sik Kim
  • Patent number: 11036415
    Abstract: A computer-implemented method, according to one embodiment, is for managing block calibration operations. The computer-implemented method includes: determining a type of calibration procedure to apply to a block of memory, and assigning the calibration type to the block. A calibration level to assign to the block is also determined, and thereafter the calibration level is assigned to the block. Moreover, the block is assigned to one of two or more calibration queues based on the calibration type and calibration level associated with the block. A different priority level is assigned to each of the calibration queues, and the priority levels determine an order in which blocks assigned to the calibration queues are calibrated.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: June 15, 2021
    Assignee: International Business Machines Corporation
    Inventors: Nikolaos Papandreou, Roman Alexander Pletka, Aaron Daniel Fry, Timothy Fisher, Nikolas Ioannou, Charalampos Pozidis, Radu Ioan Stoica, Sasa Tomic
  • Patent number: 11036638
    Abstract: A computer system monitors usage of an application on a computing device to identify one or more pre-fetch situations corresponding to a user of the computing device. The computer system determines whether the computing device is in a situation that corresponds to at least one of the identified one or more pre-fetch situations. In response to determining that the computing device is in the situation that corresponds to the at least one of the identified one or more pre-fetch situations, the computer system causes data corresponding to the application to be pre-fetched.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: June 15, 2021
    Assignee: PAYPAL, INC.
    Inventors: Cheng Tian, Braden Christopher Ericson, Titus Woo
  • Patent number: 11016904
    Abstract: A storage device includes a controller and a memory. In response to a request of a host, the controller generates: (A) a first list as a result of counting: (1) the number of first page numbers included in a first range among page numbers included in a logical address received from the host and (2) the number of second page numbers included in a second range not overlapping the first range, (B) generates a second list as a result of respectively grouping the first page numbers and the second page numbers based on the first list, and (C) translates the logical address to a physical address based on the second list and the first map data. The memory stores the first map data to be provided to the controller. The first map data matches the first page numbers and the second page numbers with respective physical addresses.
    Type: Grant
    Filed: August 17, 2019
    Date of Patent: May 25, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yongwon Cho, Hyeonwu Kim, Seok-Won Ahn
  • Patent number: 11016897
    Abstract: Disclosed aspects relate to cache management in a stream computing environment that uses a set of many-core hardware processors to process a stream of tuples by a plurality of processing elements which operate on the set of many-core hardware processors. The stream of tuples to be processed by the plurality of processing elements which operate on the set of many-core hardware processors may be received. A tuple-processing hardware-route on the set of many-core hardware processors may be determined based on a cache factor associated with the set of many-core hardware processors. The stream of tuples may be routed based on the tuple-processing hardware-route on the set of many-core hardware processors. The stream of tuples may be processed by the plurality of processing elements which operate on the set of many-core hardware processors.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: May 25, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Cook, Cory J. Kleinheksel, David M. Koster, Jason A. Nikolai
  • Patent number: 11016700
    Abstract: Accumulating application-level statistics in a storage system that includes a plurality of block storage devices, including: identifying, from data stored on a block storage device, one or more sub-regions of the data stored on the block storage device that are associated with an application; and compiling, from statistics maintained for each of the one or more sub-regions of the stored data associated with the application, cumulative statistics for the application.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: May 25, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Steven Hodgson, Ronald Karr
  • Patent number: 11010061
    Abstract: Cross point memory architectures, devices, systems, and methods are disclosed and described, and can include a cross point memory core subsystem having increased bandwidth that is scalable. The memory core can include a plurality of independently operating partitions, each comprising a plurality of cross point memory arrays.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Rajesh Sundaram, Albert Fazio, Derchang Kau, Shekoufeh Qawami
  • Patent number: 10997026
    Abstract: A method is disclosed for destaging data to a storage device set that is arranged to maintain M replicas of the data, the storage device set having M primary storage devices and N secondary storage devices, the method comprising: detecting a destage event; and in response to the destage event, destaging the data item that is stored in a journal, the destaging including: issuing M primary write requests for storing the data item, each of the M primary write requests being directed to a different one of the M primary storage devices; in response to detecting that L of the primary write requests have failed, issuing L secondary write requests for storing the data item, each of the L secondary write requests being directed to a different secondary storage device; updating a bitmap to identify all primary and secondary storage devices where the data item has been stored.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: May 4, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Lior Kamran, Alex Soukhman, Hillel Costeff
  • Patent number: 10990531
    Abstract: Systems, apparatuses and methods may provide for technology that in response to one or more of an installation of an application or a modification to the application, generates a lookup key based on a first file that is associated with the application, determines that the lookup key is to be transmitted to a server, and determines whether to store at least a portion of the first file in a memory cache based on a first frequency indicator associated with the first file from the server.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: April 27, 2021
    Assignee: Intel Corporation
    Inventors: Fredrick Odhiambo, Maximillan Domeika
  • Patent number: 10983875
    Abstract: Recovery points can be used for replicating a virtual machine and reverting the virtual machine to a different state. A filter driver can monitor and capture input/output commands between a virtual machine and a virtual machine disk. The captured input/output commands can be used to create a recovery point. The recovery point can be associated with a bitmap that may be used to identify data blocks that have been modified between two versions of the virtual machine. Using this bitmap, a virtual machine may be reverted or restored to a different state by replacing modified data blocks and without replacing the entire virtual machine disk.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: April 20, 2021
    Assignee: Commvault Systems, Inc.
    Inventors: Amit Mitkar, Andrei Erofeev, Amit Bhaskar Ausarkar, Ajay Venkat Nagrale
  • Patent number: 10983722
    Abstract: A data storage device includes a nonvolatile memory device, a storage controller and a mapping controller. The nonvolatile memory device stores an execution code that controls operations of the data storage device. The storage controller uploads and stores the execution code from the nonvolatile memory device to a host memory buffer included in an external host device, and downloads the execution code in realtime from the host memory buffer to execute the execution code that is downloaded from the host memory buffer. The mapping controller manages a mapping table including mapping relations between the execution code and host addresses of the host memory buffer at which the execution code is stored. A speed of accessing the execution code is increased and performance of the data storage device is enhanced by using the host memory buffer as storage of the execution code to control the operation of the data storage device.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: April 20, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Seok Kim, Walter Jun
  • Patent number: 10977184
    Abstract: A method for managing memory access for implementing at least one layer of a convolutional neural network is provided. The method comprises predicting an access procedure in relation to a portion of memory based on a characteristic of the convolutional neural network. In response to the prediction, the method comprises performing an operation to obtain and store a memory address translation, corresponding to the portion of memory, in storage in advance of the predicted access procedure. An apparatus is provided comprising at least one processor and storage. The apparatus is configured to predict an access procedure in relation to a portion of memory which is external to the processor. In response to the prediction, the apparatus is configured to obtain and store a memory address translation corresponding to the portion of memory in storage in advance of the predicted access procedure.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: April 13, 2021
    Assignee: Apical Limited and Arm Limited
    Inventors: Sharjeel Saeed, Daren Croxford, Graeme Leslie Ingram
  • Patent number: 10969980
    Abstract: A processor includes a processing core; a filter register to store a first permissions filter; and a memory management unit (MMU), coupled to the processing core, the filter register and a first peripheral device associated with the first permissions filter, wherein the MMU comprises a logic circuit to manage a shared page table comprising entries corresponding to the processing core and the first peripheral device, wherein the logic circuit is to; receive a memory access request for a first page of memory from the first peripheral device; determine whether the set of permission bits of the first entry match a first combination of bits of the first permissions filter; grant the memory access request if the set of permission bits match the first combination of bits of the first permissions filter; and cause a page fault if the set of permission bits do not matching the first combination of bits.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: David Hansen, Ashok Raj
  • Patent number: 10949352
    Abstract: A cache is shared by a first and second processor, and is divided into a first cache portion corresponding to a first requestor identifier (ID) and a second cache portion corresponding to a second requestor ID. The first cache portion is accessed in response to memory access requests associated with the first requestor ID, and the second cache portion is accessed in response to memory access requests associated with the second requestor ID. A memory controller communicates with a shared memory, which is a backing store for the cache. A corresponding requestor ID is received with each memory access request. Each memory access request includes a corresponding access address identifying a memory location in the shared memory and a corresponding index portion, wherein each corresponding index portion selects a set in a selected cache portion of the first and second cache portions selected based on the received corresponding requestor ID.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: March 16, 2021
    Assignee: NXP USA, Inc.
    Inventor: Paul Kimelman
  • Patent number: 10949122
    Abstract: A computer-implemented method, according to one embodiment, includes: determining a current temperature associated with an intended storage location in memory for data in a write request, determining a percentage of first logical states included in a binary representation of the data in the received write request, selecting a write management operation in response to determining that the current temperature associated with the intended storage location is outside a predetermined range, and sending one or more instructions to perform the write management operation. Moreover, the write management operation corresponds to the determined percentage of first logical states included in the binary representation. Other systems, methods, and computer program products are described in additional embodiments.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: March 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Saravanan Sethuraman, Venkata K. Tavva, Adam J. McPadden, Hillery Hunter