Patents Examined by Shawn X. Gu
  • Patent number: 10810086
    Abstract: A method includes emulating an Enhanced Application Module Redundancy (EAM-R) system that includes a primary EAM-R board and a secondary EAM-R board. Emulating the EAM-R system includes detecting that data received from a sensor has been written to a memory block associated with the primary EAM-R board, and sending instructions to a secondary computing device to write a copy of the data to a same memory block in the secondary computing device that is associated with the secondary EAM-R board. The EAM-R system is emulated in an emulation system that includes at least one network connection. The emulation system does not include a physical primary EAM-R board or a physical secondary EAM-R board.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: October 20, 2020
    Assignee: Honeywell International Inc.
    Inventor: Elliott Rachlin
  • Patent number: 10809918
    Abstract: Options for handling write operations may be selected based on a determined probability that a read operation for a portion of data will occur while the data portion is still in an I/O cache as a result of a write operation. As used herein, a “read-after-write event (“RAW”) is an occurrence of a read operation for a portion of data while the data portion is still in an I/O cache as a result of a write operation. The probability of a RAW may be determined by applying Bayesian inference, and may include applying exponential smoothing to calculations made on historical I/O information so that more recent I/O events have greater weight in determining RAW probability. Based on the determined RAW probability, write data may either be journaled in a write journal or written to a cache slot and de-staged to a physical storage device as part of write-in-place processing.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: October 20, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Owen Martin, Mark J. Halstead, William R. Smith-Vaniz
  • Patent number: 10809923
    Abstract: According to one embodiment, a hardware-based processing node of a plurality of hardware-based processing nodes in an object memory fabric can comprise a memory module storing and managing a plurality of memory objects in a hierarchy of the object memory fabric. Each memory object can be created natively within the memory module, accessed using a single memory reference instruction without Input/Output (I/O) instructions, and managed by the memory module at a single memory layer. The object memory fabric can utilize a memory fabric protocol between the hardware-based processing node and one or more other nodes of the plurality of hardware-based processing nodes to distribute and track the memory objects across the object memory fabric. The memory fabric protocol can be utilized across a dedicated link or across a shared link between the hardware-based processing node and one or more other nodes of the plurality of hardware-based processing nodes.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: October 20, 2020
    Assignee: Ultrata, LLC
    Inventors: Steven J. Frank, Larry Reback
  • Patent number: 10802751
    Abstract: A memory system may include: a memory device comprising a plurality of channels, a plurality of dies coupled to the respective channels, and a plurality of super blocks; and a controller suitable for controlling the memory device, wherein the controller includes: a detector suitable for searching for a first available reserved block in a first die, when a bad block has occurred in the first die which is coupled to a first channel and belongs to a first super block group, and searching for a second available reserved block in a second die which is coupled to the first channel and belongs to a second super block group when the first available reserved block is not present in the first die; and an assignor suitable for replacing the bad block with the second available reserved block when the second available reserved block is present.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: October 13, 2020
    Assignee: SK hynix Inc.
    Inventors: Duck-Hoi Koo, Yong-Tae Kim
  • Patent number: 10802570
    Abstract: An information processing apparatus is equipped with a storage and obtains a remaining life time of the information processing apparatus, sets a minimum off/on time interval for a power supply of an equipped storage based on the obtained remaining life time of the information processing apparatus and a remaining number of times of power supply of the storage can be turned off/on, and controls so that a transition is made to a sleep mode in a state in which the minimum off/on time interval for the power supply of the storage that is set is ensured.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: October 13, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Xiaoli Wang
  • Patent number: 10795825
    Abstract: An electronic device includes at least one compression-decompression functional block and a hierarchy of cache memories with a first cache memory and a second cache memory. The at least one compression-decompression functional block receives data in an uncompressed state, compresses the data using one of a first compression or a second compression, and, after compressing the data, provides the data to the first cache memory for storage therein. When the data is retrieved from the first cache memory to be stored in the second cache memory, when the data is compressed using the first compression, the compression-decompression functional block decompresses the data to reverse effects of the first compression on the data, thereby restoring the data to the uncompressed state and provides the data compressed using the second compression or in the uncompressed state to the second cache memory for storage therein.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: October 6, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Matthew J. Tomei, Philip B. Bedoukian, Shomit N. Das
  • Patent number: 10776035
    Abstract: A storage system and storage control method are provided in which a plurality of volumes to be processed by a storage control unit are distributed and evacuated in a normal storage control unit without recovering redundancy of the storage control unit having decreased redundancy, and the storage control unit itself having the decreased redundancy is deleted after the evacuating is completed, and thus reservation information processing resources for guaranteeing recoverability of the redundancy become unnecessary.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: September 15, 2020
    Assignee: HITACHI, LTD.
    Inventors: Kenta Sato, Akira Deguchi, Tomohiro Kawaguchi
  • Patent number: 10769071
    Abstract: Apparatuses and methods related to providing coherent memory access. An apparatus for providing coherent memory access can include a memory array, a first processing resource, a first cache line and a second cache line coupled to the memory array, a first cache controller, and a second cache controller. The first cache controller coupled to the first processing resource and to the first cache line can be configured to provide coherent access to data stored in the second cache line and corresponding to a memory address. A second cache controller coupled through an interface to a second processing resource external to the apparatus and coupled to the second cache line can be configured to provide coherent access to the data stored in the first cache line and corresponding to the memory address.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: September 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Timothy P. Finkbeiner, Troy D. Larsen
  • Patent number: 10761941
    Abstract: Various examples are directed to systems and methods for backing up data. A tracking utility may receive a start request and then enter a holding mode until a first modifiable or writable snapshot is created. The tracking utility can track such a first snapshot and determine if any modifications such as writes have been made to the first snapshot. If the first snapshot has not been modified it can be backed up using a read only snapshot scheme. If the first snapshot has been modified, a record of the modifications thereto are used to update the frozen changes and the current changes. The resulting or finalized snapshot is generated and includes all of the modifications, modifications 1 to N made to the first snapshot. This process can be repeated for one or more or all of the modifiable or writable snapshots.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: September 1, 2020
    Assignee: ACRONIS INTERNATIONAL GMBH
    Inventors: Andrei Redko, Stanislav Protasov, Serguei M. Beloussov
  • Patent number: 10754574
    Abstract: Technologies are provided for storing data in a storage device based on an associated attribute or attributes. A storage device can be configured to write data to a storage location of the storage device based on an associated attribute. The attribute can describe one or more storage-related requirements of the data. The storage device can identify one or more storage locations where the data can be stored that meet the storage-related requirements described by the attribute. A host computer can transmit an updated attribute for the data to the storage device to reflect new storage-related requirements for the data. The storage device can write the data to a new storage location that meets the new requirements. A mapping table can be maintained that associates a logical identifier for the data with the actual storage location where the data is stored.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: August 25, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Keun Soo Jo, Munif M. Farhan, Seth William Markle
  • Patent number: 10754571
    Abstract: Provided herein may be a storage device and a method of operating the storage device. The storage device includes a memory device including a plurality of system blocks; and a memory controller configured to perform a read reclaim operation of copying system data stored in a selected system block to another one of the plurality of system blocks using information obtained during loading of the system data into the selected system block.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: August 25, 2020
    Assignee: SK hynix Inc.
    Inventor: Jang Hwan Jun
  • Patent number: 10754548
    Abstract: A data storage device is provided. The data storage device includes a flash memory and a controller. The flash memory stores a firmware. The firmware includes a plurality of mode page settings, and each mode page setting includes a plurality of mode parameters. The controller receives a mode selection command and a data out message arranged to rewrite a first mode page setting among the plurality of mode page settings from a host. The controller determines whether the data out message will change the mode parameters which cannot be rewritten in the first mode page setting according to the data out message. When the data out message will not change the mode parameters which cannot be rewritten in the first mode page setting, the controller determines whether a plurality of new mode parameters are kept in the flash after the data storage device is turned off.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: August 25, 2020
    Assignee: SILICON MOTION, INC.
    Inventors: Te-Kai Wang, Yu-Da Chen
  • Patent number: 10747673
    Abstract: Embodiments described herein provide a system for facilitating cluster-level cache and memory in a cluster. During operation, the system presents a cluster cache and a cluster memory to a first application running on a first compute node in the cluster. The system maintains a first mapping between a first virtual address of the cluster cache and a first physical address of a first persistent storage of the first compute node. The system maintains a second mapping between a second virtual address of the cluster memory and a second physical address of a second persistent storage of a first storage node of the cluster. Upon receiving a first memory allocation request for cache memory from the first application, the system allocates a first memory location corresponding to the first physical address. The first application can be configured to access the first memory location based on the first virtual address.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: August 18, 2020
    Assignee: Alibaba Group Holding Limited
    Inventor: Shu Li
  • Patent number: 10740014
    Abstract: The present invention provides a memory size determining method which includes: writing a magic string into an initial location of the memory space of a memory; performing a first time reading with a first range on the memory, and if the magic string is not found in the first time reading, performing a second time reading with a second range on the memory, until the magic string is found; and if the magic string is found in the N-th time reading, determining the N-th range corresponding to the N-th time reading as the memory size, wherein N is an positive integer larger than or equal to 1.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: August 11, 2020
    Assignee: JMicron Technology Corp.
    Inventor: Cheng-Huan Wu
  • Patent number: 10732873
    Abstract: A data store is accessed that stores a collected historical record of performance metrics for input/output operations executed at a storage device that is part of a group of storage devices that are configured to provide a fault resiliency function. A performance profile is determined for the selected storage device based on selected performance metrics of the historical record. A difference between the performance profile for the storage device and a characteristic performance profile for similar storage devices is determined. When the difference exceeds a predetermined deviance threshold, selected I/O requests designated for the selected storage device are redirected to another device of the group of storage devices.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: August 4, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Scott Chao-Chueh Lee, Bryan Stephen Matthew, Vinod R. Shankar
  • Patent number: 10733098
    Abstract: Example storage systems, storage devices, and methods provide a write group journal for identifying incomplete writes. Related write request indicators are stored in a non-volatile journal in a solid state drive to identify a related write group and indicate whether the related write group has been stored in storage locations corresponding to physical page addresses. An event notification is sent to a host system when the related write request indicator indicates that the group was incomplete at the time of a data loss event.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: August 4, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Kapil Sundrani, Karimulla Sheik
  • Patent number: 10719453
    Abstract: Each entry of a set associative address translation cache (ATC) stores address translation data (ATD) used by processing circuitry when converting a virtual address into a corresponding physical address. The processing circuitry operates in multiple contexts, and each entry has an associated context identifier identifying the context to which the ATD therein applies. A masking structure comprises at least one mask storage and, for each mask storage, an associated context storage. Each mask storage provides a mask field for each set of the ATC. Control circuitry responds to a maintenance request, specifying a given context and requiring a maintenance operation to be performed in respect of each entry of the ATC that stores ATD applying to the given context, by setting each mask field in a selected mask storage, storing an indication of the given context in the associated context storage, and issuing a response to a request source.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: July 21, 2020
    Assignee: Arm Limited
    Inventor: Abhishek Raja
  • Patent number: 10719253
    Abstract: A method comprises, in an information processing system implementing data deduplication and compression, wherein the information processing system comprises a set of data storage devices, receiving by at least one of the data storage devices comprising a processing device an instruction from the information processing system to perform at least a portion of a compression operation. The method also comprises performing the portion of the compression operation in response to the instruction, and sending a result of the performed portion of the compression operation to the information processing system.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: July 21, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Amitai Alkalay, Zvi Schneider, Assaf Natanzon
  • Patent number: 10712972
    Abstract: In one non-limiting embodiment, a method is disclosed for performing a storage device operation on a die is provide having steps of choosing a storage device operation to perform, estimating which die is related to the storage device operation chosen to be performed and performing the storage device operation at the die based on the estimating.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: July 14, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Amir Shaharabany, Hadas Oshinsky
  • Patent number: 10705957
    Abstract: A cache memory stores a cache line associated with a coherence state field set to a first modified coherence state. The cache memory implements a default first coherence state update policy in which the cache memory is biased to retain write authority for the cache line. Responsive to a store request, the cache memory updates data of the cache line. If the store request indicates a change from the default first coherence state update policy, the cache memory updates the coherence state field from the first modified coherence state to a second modified coherence state in which the cache memory is biased to transfer write authority for the cache line. If the store request does not indicate a change from the default first coherence state policy, the cache memory refrains from updating the coherence state field from the first modified coherence state.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: July 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Derek E. Williams, Guy L. Guthrie