Patents Examined by Shawn X. Gu
  • Patent number: 11704044
    Abstract: Modifying a clone image of a dataset, including: generating, based on metadata describing one or more updates to a dataset, a tracking copy of replica data on a target data repository; generating, after receiving an indication to begin accepting modifications to the tracking copy of the replica data, a cloned image of the dataset that is modifiable without modifying the tracking copy of the replica data; and responsive to a storage operation directed to the target data repository, modifying the cloned image of the dataset without modifying the tracking copy of the replica data.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: July 18, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: David Grunwald, Thomas Gill, Ronald Karr, John Colgrove, Larry Touchette, Lawrence Mertes
  • Patent number: 11698859
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to receive a first request to allocate a direct swap file associated with an application stored in a system memory on a persistent storage media, and map a linear and continuous space of the persistent storage media to the direct swap file associated with the application in response to the first request. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: July 11, 2023
    Assignee: SK Hynix NAND Product Solutions Corp.
    Inventor: Mariusz Barczak
  • Patent number: 11698838
    Abstract: Disclosed herein is a technique to automatically re-bind applications and storage volumes during recovery from planned outage or platform failure and disaster recovery. Such implementations can involve managing volume management information that maps volume claim information with a logical volume identifier associated with persistent volume information; and for receipt of a request for a new volume, referencing the volume management information to retrieve an associated logical volume identifier and the persistent volume information based on the volume claim information associated with the request; and providing the retrieved persistent volume information to a volume provisioning function.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: July 11, 2023
    Assignee: HITACHI, LTD.
    Inventor: Naruki Kurata
  • Patent number: 11698731
    Abstract: Responsive to a power-on of a memory device, an elapsed power-off time is identified based on a difference between a time at which the power-on occurred and a time at which a previous power-off of the memory device occurred. Responsive to a determination that the elapsed power-off time satisfies the elapsed time threshold criterion, a request to perform a first write operation on a memory unit of the memory device since power on is received, a performance parameter associated with the memory unit of the memory device is changed to a first parameter value that corresponds to a reduced performance level, and the write operation is performed on the memory unit of the memory device in accordance with the first parameter value that corresponds to the reduced performance level. Responsive to completion of the write operation, the performance parameter is changed to a value that corresponds to a normal performance level.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: July 11, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Murong Lang, Zhenming Zhou
  • Patent number: 11687453
    Abstract: Cache-based trace logging using tags in an upper cache level. A processor influxes a cache line into a first cache level from an upper second cache level. Influxing the cache line into the first cache level includes, based on the first cache level being a recording cache, the processor reading a tag that is (i) stored in the second cache level and (ii) associated with the cache line. Based on reading the tag, the processor determines whether a first value of the cache line within the second cache level has been previously captured by a trace. The processor performs one of (i) when the first value is determined to have been previously logged, following a logged value logic path when influxing the cache line; or (ii) when the first value is determined to have not been previously logged, following a non-logged value logic path when influxing the cache line.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: June 27, 2023
    Inventors: Jordi Mola, Thomas Philip Speier
  • Patent number: 11688431
    Abstract: In one aspect of tape repositioning management in accordance with the present description, in response to loading a tape in a tape drive, mounting the tape linear tape file system (LTFS) is initiated including reading an index partition on the tape to extract metadata for mounting the tape LTFS, and prior to accessing a data area of the tape in response to any application access request, the tape is repositioned within a data partition to read a vHRTD (virtual High Resolution Tape Directory) recorded in an EOD (End of Data) portion such as an EOD data set, for example, of the data partition. The EOD portion is read to retrieve the vHRTD to facilitate application requested accesses to the tape. In one embodiment, repositioning and stopping the tape at the beginning of the data partition after reading the index partition containing metadata is bypassed.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: June 27, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tsuyoshi Miyamura, Atsushi Abe, Setsuko Masuda
  • Patent number: 11675706
    Abstract: A programmable switch includes at least one memory configured to store a cache directory for a distributed cache, and circuitry configured to receive a cache line request from a client device to obtain a cache line. The cache directory is updated based on the received cache line request, and the cache line request is sent to a memory device to obtain the requested cache line. An indication of the cache directory update is sent to a controller for the distributed cache to update a global cache directory. In one aspect, the controller sends at least one additional indication of the update to at least one other programmable switch to update at least one backup cache directory stored at the at least one other programmable switch.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: June 13, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Marjan Radi, Dejan Vucinic
  • Patent number: 11669411
    Abstract: A computer program product, system, and computer implemented method for management of a consolidated database and implementing pluggable database recovery with redo filtering in a consolidated database according to some embodiments. Generally, the process includes ongoing activities that maintain activity logs and summarize the activity for respective activity logs (e.g., in an activity vector maintained in a consolidated database catalog). In some embodiments, event-based activities corresponding to recovery processes are triggered by an administrator or an automated process, completed and then do not occur again until another triggering event. The event-based activities can leverage the summary information to quickly determine which online activity logs are relevant to the type of recovery operation for a particular pluggable database.
    Type: Grant
    Filed: December 6, 2020
    Date of Patent: June 6, 2023
    Assignee: Oracle International Corporation
    Inventors: Giridhar Ravipati, Yunrui Li, Kumar Rajamani, Muthu Olagappan
  • Patent number: 11669638
    Abstract: A method includes receiving an object from a client as part of a data ingestion process, directing the object to an object access microservice, providing a copy of the object to a masker worker microservice, masking the copy of the object to create a masked object, and the masking of the copy of the object is performed inline prior to storage of the object, deduplicating the object, and storing the masked object and the object in storage.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: June 6, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Kimberly R. Lu, Joseph S. Brandt, Philip N. Shilane
  • Patent number: 11669444
    Abstract: According to one embodiment, a computing system transmits to a storage device a write request designating a first logical address for identifying first data to be written and a length of the first data. The computing system receives from the storage device the first logical address and a first physical address indicative of both of a first block selected from blocks except a defective block by the storage device, and a first physical storage location in the first block to which the first data is written. The computing system updates a first table which manages mapping between logical addresses and physical addresses of the storage device and maps the first physical address to the first logical address.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: June 6, 2023
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Patent number: 11663132
    Abstract: A technique is provided for prefetching data items. An apparatus has a storage structure with a plurality of entries to store data items. The storage structure is responsive to access requests from processing circuitry to provide access to the data items. The apparatus has prefetch circuitry to prefetch data and correlation information storage to store correlation information for a plurality of data items. The correlation information identifies, for each of the plurality of data items, one or more correlated data items. The prefetch circuitry is configured to monitor the access requests from the processing circuitry. In response to detecting a hit in the correlation information storage for a particular access request that identifies a requested data item for which the correlation information storage stores correlation information, the prefetch circuitry is configured to prefetch the one or more correlated data items identified by the correlation information for the requested data item.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: May 30, 2023
    Assignee: Arm Limited
    Inventors: Joseph Michael Pusdesris, Jacob Martin Degasperis, Alexander Cole Shulyak
  • Patent number: 11656981
    Abstract: Methods and systems related to memory reduction in a system by oversubscribing physical memory shared among compute entities are provided. A portion of the memory includes a combination of a portion of a first physical memory of a first type and a logical pooled memory associated with the system. A logical pooled memory controller is configured to: (1) track both a status of whether a page of the logical pooled memory allocated to any of the plurality of compute entities is a known-pattern page and a relationship between logical memory addresses and physical memory addresses associated with any allocated logical pooled memory, and (2) allow the write operation to write data to any available space in the second physical memory of the first type only up to an extent of physical memory that corresponds to the portion of the logical pooled memory previously allocated to the compute entity.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: May 23, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Monish Shantilal Shah, Lisa Ru-Feng Hsu, Daniel Sebastian Berger
  • Patent number: 11656955
    Abstract: A system includes one or more source memory devices of a source computing environment that store a database comprising data files grouped in a plurality of file groups, wherein each of a plurality of data tables of the source computing environment includes data from one or more of the data files grouped into one or more of the file groups, one or more target memory devices of a target computing environment and at least one processor configured to calculate a number of read operations per megabyte (MB) for a data table, a number of write operations per MB, obtain an importance index of the table, weight the reads per MB, writes per MB and the importance index by respective user-defined weights, determine a criticality index of the table, calculate a value coefficient of the table, and assign a data file based on the value coefficient of the table.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: May 23, 2023
    Assignee: Bank of America Corporation
    Inventors: Praveen Kumar Trivedi, Venugopala Rao Randhi, Anshuman Mohanty, Ritesh Kumar Dash
  • Patent number: 11657000
    Abstract: Disclosed is a memory system including: a memory device including a plurality of memory blocks; an address management component suitable for generating an address map table by sequentially mapping a logical address of write data to physical addresses of the memory blocks, in response to a write command; and a read/write control component suitable for writing the write data to a super memory block including pages of each of the memory blocks, based on the address map table, wherein the address management component maps a logical address of invalidation data which is designated by a host, to a physical address of a first memory block of the memory blocks in the address map table.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: May 23, 2023
    Assignee: SK hynix Inc.
    Inventor: Eu Joon Byun
  • Patent number: 11656988
    Abstract: A memory device and an operation method thereof are provided. The memory device includes: a plurality of page buffers, storing an input data; a plurality of memory planes coupled to the page buffers, based on received addresses of the memory planes, a plurality of weights stored in the memory planes, the memory planes performing bit multiplication on the weights and the input data in the page buffers in parallel to generate a plurality of bit multiplication results in parallel, the bit multiplication results stored back to the page buffers; and at least one accumulation circuit coupled to the page buffers, for performing bit accumulation on the bit multiplication results of the memory planes in parallel or in sequential to generate a multiply-accumulate (MAC) operation result.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: May 23, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Han-Wen Hu, Yung-Chun Li, Bo-Rong Lin, Huai-Mu Wang
  • Patent number: 11644985
    Abstract: Methods, systems, and devices for a low-speed memory operation are described. A controller associated with a memory device may, for example, identify a clock mode for a system clock and determine that a speed of the system clock is below a threshold. The controller may generate (or cause to be generated) an internal data clock signal having a shorter period than an external data clock signal (which may have a speed based on the system clock speed). Also, the controller may use, instead of the external data clock signal, the internal data clock signal to generate data from the memory device, which may provide reduced latency. Further, the controller may deactivate (or cause to be deactivated) an external data clock that generates the external data clock signal.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: May 9, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Kang-Yong Kim
  • Patent number: 11645210
    Abstract: Embodiments are disclosed for performing cache aware searching. In response to a search query, a first bucket and a second bucket in remote storage for processing the search query. A determination is made that a first file in the first bucket is present in a cache when the search query is received. In response to the search query, a search is performed using the first file based on the determination that the first file is present in the cache when the search query is received, and the search is performed using a second file from the second bucket once the second file is stored in the cache.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: May 9, 2023
    Assignee: Splunk Inc.
    Inventors: Ledion Bitincka, Alexandros Batsakis, Paul J. Lucas, Nicholas Robert Romito
  • Patent number: 11635900
    Abstract: A method includes receiving signaling indicative of performance of a shutdown operation involving a memory device to a controller resident on the memory device; initiating a power off sequence in response to the received signaling, wherein the power off sequence includes execution of instructions corresponding to a plurality of routines; and writing data comprising respective shutdown signatures associated with execution of the plurality of routines to a media associated with the memory device upon completion of each of one or more of the plurality of routines, wherein the media is bit-addressable or byte-addressable.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: April 25, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Kelsey J. Dobner
  • Patent number: 11630783
    Abstract: Provided are a computer product, method, and system to virtualize target system storage resources as virtual target storage resources. Target storage resources available at a target system are discovered over a network. A configuration is determined of virtual target storage resources mapping to the target storage resources for a host node. The configuration is registered with a virtual target. The configuration maps the virtual target storage resources to the target storage resources at the target system and an access control list of the host node allowed to access the virtual target storage resources. A query is received from the host node for the target storage resources the host node is permitted to access according to the access control list. Host discovery information is returned to the requesting host node indicating the virtual target storage resources the requesting host node is provisioned to access from the virtual target.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: April 18, 2023
    Assignee: Intel Corporation
    Inventors: Jay E. Sternberg, Phil C. Cayton, James P. Freyensee, Dave B. Minturn
  • Patent number: 11625325
    Abstract: A server includes a data cache for storing data objects requested by users logged in under different user roles. Different user roles may have different permissions to access individual fields within a data object. When a cache miss occurs, the cache may begin loading portions of a requested data object from various data sources. Instead of waiting for the entire object to load to change the object state to “valid,” the cache may incrementally update the state through various levels of validity based on the user role of the request. When a portion of the data object used by a low-level user role is received, the object state can be upgraded to be valid for that user role while data for higher-level user roles continues to load. The portion of the data object can then be sent to the low-level user roles without waiting for the rest of the data object to load.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: April 11, 2023
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Yuvaraj Chandrasekaran, Mihir Kumar Das, Pushpander Singh, Lawrence Lindsey