Patents Examined by Shawn X. Gu
  • Patent number: 10698618
    Abstract: Methods, computing systems and computer program products implement embodiments of the present invention that include defining a plurality of failure domains for sets of storage devices in a storage facility, and defining, using the failure domains, one or more limitations for distributing data on the storage devices. Upon identifying a data distribution configuration for a software defined storage system that is compliant with the one or more limitations, the identified data distribution configuration can be presented to a user. The failure domains may include physical failure domains, logical failure domains, or a combination of physical and logical failure domains, and the limitations may include mandatory limitations or a combination of mandatory and non-mandatory limitations.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: June 30, 2020
    Assignee: INTERNATIONAL BUISNESS MACHINES CORPORATION
    Inventors: Zah Barzik, Lior Chen, Michael Keller, Rivka M. Matosevich
  • Patent number: 10698818
    Abstract: Systems and techniques for performing a data transaction are disclosed that provide data redundancy using two or more cache devices. In some embodiments, a data transaction is received by a storage controller of a storage system from a host system. The storage controller caches data and/or metadata associated with the data transaction to at least two cache devices that are discrete from the storage controller. After caching, the storage controller provides a transaction completion response to the host system from which the transaction was received. In some examples, each of the at least two cache devices includes a storage class memory. In some examples, the storage controller caches metadata to the at least two cache devices and to a controller cache of the storage controller, while data is cached to the at least two cache devices without being cached in the controller cache.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: June 30, 2020
    Assignee: NETAPP, INC.
    Inventors: Brian McKean, Gregory Friebus, Sandeep Kumar R. Ummadi, Pradeep Ganesan
  • Patent number: 10698819
    Abstract: A memory system may include: a nonvolatile memory device including a memory cell array and a page buffer coupled to the memory cell array; and a controller configured to interface with the nonvolatile memory device, wherein the controller moves descriptors on a cache command from a command queue to a cache queue, the cache command being transferred to the nonvolatile memory device, and selectively moves the descriptors moved to the cache queue to a response queue.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: June 30, 2020
    Assignee: SK hynix Inc.
    Inventor: Beom Rae Jeong
  • Patent number: 10691365
    Abstract: A method of migrating memory includes protecting, by a hypervisor, a first memory page from write operations, the first memory page being used for direct memory access (DMA) by a device and stored at a guest memory address that maps to a first host-physical address. A second memory page is stored at the first host-physical address, and the device is allowed DMA in an input/output memory management unit (IOMMU). The method also includes allocating a third memory page at a second host-physical address and copying data stored at the second memory page to the third memory page. The method further includes updating a mapping including the guest memory address to reference the second host-physical address and detecting that the first memory page is protected from write operations by the device. The method further includes pinning the second memory page to main memory of the host machine and storing the mapping.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: June 23, 2020
    Assignee: Red Hat, Inc.
    Inventors: Michael Tsirkin, Andrea Arcangeli
  • Patent number: 10684782
    Abstract: One example method includes receiving an IO associated with a process initiated by an application, where the IO is identified by a tag that corresponds to the process. The method further includes saving the tag on a device that is an element of a storage group (SG) that is specific to the application, and correlating the tag with a data protection process that is associated with the application. When a request is received to perform an SG protection process, the SG protection process is performed on the tagged device.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: June 16, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Arieh Don, Jehuda Shemer, Yaron Dar
  • Patent number: 10678696
    Abstract: Embodiments are disclosed for a prefetching method that may include copying, in response to a search query, a first bucket from a remote storage to a cache. The first bucket may include first data associated with the search query. The method may further include identifying a first file type associated with a first file in the first bucket. The first file may be associated with a usage status. The method may further include accessing, based on the search query, a second bucket from the remote storage. The second bucket may include second data associated with the search query. The method may further include identifying a second file in the second bucket having the first file type, and copying, in response to the usage status indicating that the first file was used in processing the search query, the second file from the remote storage to the cache.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: June 9, 2020
    Assignee: Splunk, Inc.
    Inventors: Ledion Bitincka, Alexandros Batsakis, Paul J. Lucas, Nicholas Robert Romito
  • Patent number: 10678587
    Abstract: A computer system including one or more processors and persistent, word-addressable memory implements a persistent atomic multi-word compare-and-swap operation. On entry, a list of persistent memory locations of words to be updated, respective expected current values contained the persistent memory locations and respective new values to write to the persistent memory locations are provided. The operation atomically performs the process of comparing the existing contents of the persistent memory locations to the respective current values and, should they match, updating the persistent memory locations with the new values and returning a successful status. Should any of the contents of the persistent memory locations not match a respective current value, the operation returns a failed status. The operation is performed such that the system can recover from any failure or interruption by restoring the list of persistent memory locations.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: June 9, 2020
    Assignee: Oracle International Corporation
    Inventors: Virendra J. Marathe, Matej Pavlovic, Alex Kogan, Timothy L. Harris
  • Patent number: 10678474
    Abstract: A computing system using low-fat pointers, including: a memory configured to be accessed by the low-fat pointers; a processing core configured to access the memory; an interrupt controller configured to receive interrupts and to communicate interrupts to processes running on the processing core; and a memory safety peripheral configured to receive a pointer request, wherein the pointer is a low-fat pointer and to verify that the pointer request is within required memory bounds.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: June 9, 2020
    Assignee: NXP B.V.
    Inventors: Marcel Medwed, Jan Hoogerbrugge, Ventzislav Nikov
  • Patent number: 10678466
    Abstract: Migrating data from a first storage device to a second storage device includes coupling a host computer to the storage devices, causing the host computer to transition from performing I/O operations with the first storage device to performing I/O operations with the second storage device by modifying metadata used for I/O operations to change a mapping of logical devices to physical devices, migrating data from the first storage device to the second storage device independently of any I/O operations by the host, and acknowledging a data write operation from the host only after the data has been successfully written to both the first storage device and the second storage device. Modifying metadata may include changing control block information in device drivers. The data may be written by the host to the second storage device only and the data may be copied from the second storage device to the first storage device.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: June 9, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Douglas E. LeCrone, Martin Feeney, Jeffrey L. Jones
  • Patent number: 10671528
    Abstract: A memory system may comprise: a memory device including a plurality of memory dies; and a controller including a first memory, Wherein the controller may store data segments of user data, corresponding to a plurality of commands received from a host, in the first memory, controls the memory device to sequentially store the data segments in the memory dies through interleaving, may update map segments of map data corresponding to storage of the data segments in the memory dies, may store the map segments in the first memory, controls the memory device to store the map segments stored in the first memory in the memory dies, and may assist the host in storing the map segments, stored in the first memory, in a second memory in the host.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: June 2, 2020
    Assignee: SK hyniX Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 10671540
    Abstract: Embodiments are disclosed for performing cache aware searching. In response to a search query, a first bucket and a second bucket in remote storage for processing the search query. A determination is made that a first file in the first bucket is present in a cache when the search query is received. In response to the search query, a search is performed using the first file based on the determination that the first file is present in the cache when the search query is received, and the search is performed using a second file from the second bucket once the second file is stored in the cache.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: June 2, 2020
    Assignee: Splunk, Inc.
    Inventors: Ledion Bitincka, Alexandros Batsakis, Paul J. Lucas, Nicholas Robert Romito
  • Patent number: 10671319
    Abstract: A memory device includes first and second bank groups, an internal command generator, and an address input/output circuit. Each of the bank groups includes a plurality of banks. The internal command generator generates and outputs internal commands to a first target bank. The internal commands are generated based on a command from a memory controller for controlling a memory operation of the first target bank. The address input/output (I/O) circuit receive a first address corresponding to the command, selects a storage path of the first address based on whether there is a bubble interval in a data burst operation interval corresponding to the first command, controls output of the first address in accordance with a time point at which each of the internal commands is output. The first address is stored in the address I/O circuit.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: June 2, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-jun Shin, Hyong-ryol Hwang
  • Patent number: 10664363
    Abstract: Embodiments of the present disclosure provide a method for a storage system, a storage system and a computer program product. The method comprises determining a first drive in a drive array is temporarily unavailable. The method further comprises setting the first drive in a frozen state. The method further comprises: in response to receiving a write request for the first drive during the frozen state, pending the write request or recording the write request in a second drive in the drive array. The method further comprises: in response to receiving a read request for the first drive during the frozen state, reconstructing data to which the read request is directed through data stored in a third drive in the drive array.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: May 26, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Bing Liu, Man Lv
  • Patent number: 10664391
    Abstract: A controller includes: a counter suitable for counting a number of valid pages in each of a plurality of blocks in a memory device as first parameter values; a block selector suitable for selecting one or more first candidate blocks, the first parameter value of each of which is within a predetermined range, and selecting a victim block among the one or more first candidate blocks; and a processor suitable for controlling the memory device to read valid data stored in the victim block and program the valid data into a target block in the memory device.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: May 26, 2020
    Assignee: SK hynix Inc.
    Inventor: Eun-Soo Jang
  • Patent number: 10657040
    Abstract: A storage device including a flash memory, and circuitry that manages a logical address and a physical address so as to be converted using a conversion table, writes a logical address and old and new information indicating a timing when the data is written, into the physical address together with the data, writes at least latest old and new information of the old and new information written in the block into a predetermined page of the block, and reestablishes the conversion table by arranging the logical address recorded in each page included in the block and the physical address corresponding to the logical address in association with each other, in chronological order of the latest old and new information read out from each block of the flash memory, at a predetermined reestablishment timing for performing reestablishment of the conversion table.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: May 19, 2020
    Assignee: BUFFALO INC.
    Inventors: Kazuki Makuni, Takayuki Okinaga, Shuichiro Azuma, Yu Nakase
  • Patent number: 10657055
    Abstract: An apparatus and method are provided for managing snoop operations. The apparatus has an interface for receiving access requests from any of N master devices that have associated cache storage, each access request specifying a memory address within memory associated with the apparatus. Snoop filter storage is provided that has a plurality of snoop filter entries, where each snoop filter entry identifies a memory portion and snoop control information indicative of the master devices that have accessed that memory portion. When an access request received at the interface specifies a memory address that is within the memory portion associated with a snoop filter entry, snoop control circuitry uses the snoop control information in that snoop filter entry to determine which master devices to subject to a snoop operation.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 19, 2020
    Assignee: Arm Limited
    Inventors: Jamshed Jalal, Mark David Werkheiser, Gurunath Ramagiri, Mukesh Patel
  • Patent number: 10657065
    Abstract: A memory having a delayed write-back to the array of data corresponding to a previously opened page allows delays associated with write-back operations to be avoided. After an initial activation opens a first page and the read/write operations for that page are complete, write-back of the open page to the array of memory cells is delayed until after completion of a subsequent activate operation that opens a new page. Techniques to force a write-back in the absence of another activate operation are also disclosed.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: May 19, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas S. Andre, Syed M. Alam, Chitra K. Subramanian, Javed S. Barkatullah
  • Patent number: 10649862
    Abstract: A computer-implemented method, according to one embodiment, includes: establishing a recovery cluster as an acting primary cluster in response to determining that a primary cluster has gone offline. In response to determining that the primary cluster is back online, the acting primary cluster is synched with the online primary cluster by: capturing a snapshot of the acting primary cluster, and pausing a normal queue of the acting primary cluster. The snapshot of the acting primary cluster is further compared with a most recent snapshot of the online primary cluster, and each difference therebetween is added to a priority queue of the acting primary cluster. Each of the differences in the priority queue are transmitted to the online primary cluster, followed by the entries in the normal queue in response to determining that each of the differences in the priority queue have been transmitted to the online primary cluster.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: May 12, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ravindra Sure, Sanjiv Kumar, Shashikant Banerjee, Karrthik K G
  • Patent number: 10642512
    Abstract: Methods, systems, and devices for a low-speed memory operation are described. A controller associated with a memory device may, for example, identify a clock mode for a system clock and determine that a speed of the system clock is below a threshold. The controller may generate (or cause to be generated) an internal data clock signal having a shorter period than an external data clock signal (which may have a speed based on the system clock speed). Also, the controller may use, instead of the external data clock signal, the internal data clock signal to generate data from the memory device, which may provide reduced latency. Further, the controller may deactivate (or cause to be deactivated) an external data clock that generates the external data clock signal.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: May 5, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kang-Yong Kim
  • Patent number: 10642524
    Abstract: Migrating data in a storage array that includes a plurality of storage devices and a plurality of write buffer devices, including: detecting, by the storage array, an occurrence of a write buffer device evacuation event associated with one or more source write buffer devices; responsive to detecting the occurrence of the write buffer device evacuation event, determining, by the storage array, whether the storage array includes at least a predetermined amount of write buffer resources in addition to the one or more source write buffer devices; and responsive to determining that the storage array includes at least a predetermined amount of write buffer resources in addition to the one or more source write buffer devices, reducing, by the storage array, write access to the one or more source write buffer devices.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: May 5, 2020
    Assignee: Pure Storage, Inc.
    Inventors: John Colgrove, Lydia Do, Ethan Miller