Patents Examined by Shawn X. Gu
  • Patent number: 10922265
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to receive a transaction request to perform a transaction with the memory, the transaction request including a synchronization indication to indicate utilization of transaction synchronization to perform the transaction. Embodiments may include sending a request to a caching agent to perform the transaction, receiving a response from the caching agent, the response to indicate whether the transaction conflicts or does not conflict with another transaction, and performing the transaction if the response indicates the transaction does not conflict with the other transaction, or delaying the transaction for a period of time if the response indicates the transaction does conflict with the other transaction.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: February 16, 2021
    Assignee: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Karthik Kumar, Nicolae Popovici, Thomas Willhalm
  • Patent number: 10915443
    Abstract: Systems and methods for allocation of overprovisioned blocks for minimizing write amplification in solid state drives are disclosed.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shirish D. Bahirat, William Akin, Aditi P. Kulkarni
  • Patent number: 10915255
    Abstract: A system according to certain aspects may include a secondary storage controller computer configured to: in response to a first instruction to obtain a first secondary copy of a first data set from a secondary storage device(s), the first instruction associated with a first restore operation: instantiate a first restore thread on a processor of the secondary storage controller computer; using the first restore thread, retrieve the first secondary copy from the secondary storage device(s); and forward the retrieved first secondary copy to a primary storage subsystem for storage; and in response to a second instruction to obtain a second secondary copy of a second data set from the secondary storage device(s), the second instruction associated with a second restore operation: using the first restore thread, retrieve the second secondary copy from the secondary storage device(s); and forward the retrieved second secondary copy to the primary storage subsystem for storage.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: February 9, 2021
    Assignee: Commvault Systems, Inc.
    Inventors: Manoj Kumar Vijayan, Saurabh Agrawal, Deepak Raghunath Attarde
  • Patent number: 10909033
    Abstract: Techniques are disclosed for allocating a global memory space defined within physical memory devices into strided memory space(s) (SMS) and partition memory space(s) (PMS). In an embodiment, a SMS is mapped across all of the devices, and a PMS is mapped to a subset of the devices to ensure resource isolation between separate PMSs. Typically, a memory space is allocated in unit sizes. When the locations mapped to most of the SMS align to an integer number of the unit size, a common boundary can be formed between the SMS and the one or more PMSs in each of the devices. Such a boundary can advantageously minimize a region of locations that are not available for allocation in the global memory spaces. In an embodiment, when a strided allocation is not an integer number of the unit size, a remainder is mapped to locations for one or more PMSs.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: February 2, 2021
    Assignee: NVIDIA Corporation
    Inventors: Kun Fang, James M. Van Dyke
  • Patent number: 10895992
    Abstract: According to one embodiment, a hardware-based processing node of a plurality of hardware-based processing nodes in an object memory fabric can comprise a memory module storing and managing a plurality of memory objects in a hierarchy of the object memory fabric. Each memory object can be created natively within the memory module, accessed using a single memory reference instruction without Input/Output (I/O) instructions, and managed by the memory module at a single memory layer. The object memory fabric can distribute and track the memory objects across the hierarchy of the object memory fabric and the plurality of hardware-based processing nodes on a per-object basis. Distributing the memory objects across the hierarchy of the object memory fabric and the plurality of hardware-based processing nodes can comprise storing, on a per-object basis, each memory object on two or more nodes of the plurality of hardware-based processing nodes of the object memory fabric.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: January 19, 2021
    Assignee: Ultrata LLC
    Inventors: Steven J. Frank, Larry Reback
  • Patent number: 10891070
    Abstract: A method for managing garbage collection in a memory subsystem, where a stream data manager writes data units from a stream of data into an allocated portion of memory composed of a plurality of blocks. The stream data manager evaluates a behavior of the stream of data to calculate the stream's efficiency, the behavior including amounts of valid data units from the stream of data in the allocated portion of memory. The stream data manager estimates a number of block stripe fills until an amount of valid data units is predicted to be within a predetermined range of a threshold value of valid data units in the block using the evaluated behavior. The stream data manager performs the estimated number of block stripe fills. The stream data manager performs the garbage collection of a first block of the plurality of blocks in response to performance of the estimated number of block stripe fills.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: January 12, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: William Akin, Shirish D. Bahirat
  • Patent number: 10884640
    Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Koushik Banerjee, Lu Liu, Sanjay Rangan, Enrico Varesi, Innocenzo Tortorelli, Hongmei Wang, Mattia Boniardi
  • Patent number: 10884664
    Abstract: A memory system includes a memory having a first executable memory cell and a compilation unit. The compilation unit is configured to receive a sequence of instructions from a host device, convert each of the sequence of instructions into an execution stream, load a first code from the execution stream into a code portion of the first executable memory cell and load a first data from the execution stream into a data portion of the first executable memory cell. The first executable memory cell is configured to apply the first code to the first data via an arithmetic and logic unit of the first executable memory cell.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: January 5, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Viacheslav Dubeyko, Luis Vitorio Cargnini
  • Patent number: 10877676
    Abstract: A storage device includes a semiconductor memory device including memory blocks; and a controller configured to control the semiconductor memory device. The semiconductor memory device stores first firmware in a first memory block among the memory blocks, and stores second firmware in a second memory block among the memory blocks. The controller includes a recovery determination circuit configured to determine whether to perform a recovery operation for at least one of the first and second firmwares, based on loading times of the first and second firmwares, cumulative loading time informations for the first and second firmwares and a booting count information; and a recovery performing circuit configured to perform the recovery operation for at least one of the first and second firmwares, based on the determination of the recovery determination circuit.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: December 29, 2020
    Assignee: SK hynix Inc.
    Inventor: Jung-Ae Kim
  • Patent number: 10866745
    Abstract: Systems and methods for automated file system capacity risk analysis include obtaining first utilization data of the file system during a plurality of series of time intervals, projecting a future utilization value for the series of time intervals, and determining a threshold utilization percentage indicative of a risk of reaching maximum capacity of the file system. In response to the projected future utilization value being equal to or greater than the threshold, calculating a rate of change of the first utilization data for each of the series of time intervals, determining a variation of the rates of change of all the series of time intervals, and in response to the variation of the rates of change being positive or the first utilization data for the last time interval being equal to or greater than the threshold, designating the file system as being at risk of reaching maximum capacity.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: December 15, 2020
    Assignee: JPMORGAN CHASE BANK, N.A.
    Inventors: J. Chris Holt, Noahal Mundt
  • Patent number: 10860260
    Abstract: Techniques manage a storage system. The techniques involve: in response to determining that a rebalance operation is to be performed, determining a source storage device and a destination storage device associated with the rebalance operation based on distribution information of segments included in stripes of the storage system across a plurality of storage devices in the storage system. The techniques further involve: determining a target segment from the source storage device, based on access information of segments in the source storage device. The techniques further involve: moving the target segment to the destination storage device. Accordingly, the rebalance operation can be performed more efficiently, and the overall performance of the storage system can be optimized.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: December 8, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Tao Xu, Hongpo Gao, Jibing Dong, Shaoqin Gong, Baote Zhuo, Jian Gao
  • Patent number: 10852994
    Abstract: Techniques are provided for compacting indirect blocks. For example, an object is represented as a structure comprising data blocks within which data of the object is stored and indirect blocks comprising block numbers of where the data blocks are located in storage. Block numbers within a set of indirect blocks are compacted into a compacted indirect block comprising a base block number, a count of additional block numbers after the base block number in the compacted indirect block, and a pattern of the block numbers in the compacted indirect block. The compacted indirect block is stored into memory for processing access operations to the object. Storing compacted indirect blocks into memory allows for more block numbers to be stored within memory.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: December 1, 2020
    Assignee: NetApp Inc.
    Inventors: Ananthan Subramanian, Kumaran Nagappan, Sriram Venketaraman, Szu-Wen Kuo, Yong Eun Cho
  • Patent number: 10838818
    Abstract: A system for achieving memory persistence includes a volatile memory, a non-volatile memory, and a processor. The processor may indicate a volatile memory range for the processor to backup, and open a memory window for the processor to access. The system further includes a power supply. The power supply may provide power for the processor to backup the memory range of the volatile memory. The processor may, responsive to an occurrence of a backup event, initiate a memory transfer using the opened memory window. The memory transfer uses the processor to move the memory range of the volatile memory to a memory region of the non-volatile memory.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: November 17, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Joseph E Foster, Thierry Fevrier, James Alexander Fuxa
  • Patent number: 10838626
    Abstract: In certain techniques, a size of a storage space in a first storage device that is allocated for write requests is determined. Write requests are issued by a control device of the storage system to store data into the first storage device and are waiting to be completed. A predetermined release rate of releasing the data stored in the first storage device to a second storage device is determined. An access speed of the first storage device is greater than that of the second storage device. A predetermined completion time of the write requests is determined based on the size of the storage space and the predetermined release rate, and in response to the predetermined completion time exceeding a predetermined time threshold, a throttling indication is transmitted to the control device such that the control device throttles issuing of a further write request for the first storage device.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: November 17, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Ruiyong Jia, Xinlei Xu, Yousheng Liu, Jian Gao, Lifeng Yang
  • Patent number: 10838650
    Abstract: The system includes a data synchronization module and a heat data module. The data synchronization module is configured to communicate with a first storage volume and a second storage volume to provide a backup for the first storage volume by synchronizing information from the first storage volume to the second storage volume. The information includes at least one of data chunks, heat map data, and first metadata relating to the first storage volume. The heat data module is coupled to the second storage volume to read the first metadata and the heat map data and adjust a location of at least one of the data chunks in the second storage volume based on the heat map data.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: November 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Duo Chen, Min Fang, Da Liu, Jinyi Pu
  • Patent number: 10831705
    Abstract: A method is used in managing migration of virtual file servers. The method migrates a virtual file server from a source storage processor to a destination storage processor in a storage system. The storage system includes the source and the destination storage processors. The virtual file server comprises a root file system, a configuration file system, and a set of user file systems. The method enables concurrent access to the root file system from both source and destination storage processors during the migration until the set of user file systems is migrated from the source storage processor to the destination storage processor.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: November 10, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Kumari Bijayalaxmi Nanda, Walter Forrester
  • Patent number: 10831400
    Abstract: According to one or more embodiments described herein, a method for pause-less garbage collection includes selecting, by a garbage collector, for garbage collection, a process thread that is executing a process. The method further includes causing a first activation frame that is associated with a first method to be scanned, either by a garbage collector thread or by the process thread that is presently executing. The method further includes instructing the process thread to subsequently scan a second pause-less activation frame that is associated with a second method from a process that the process thread is presently executing. The method further includes scanning using a garbage collector thread, a third pause-less activation frame that is associated with a third method from the process, wherein scanning a pause-less activation frame includes examining and overwriting one or more live pointers from a method corresponding to said pause-less activation frame being scanned.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Kelvin D. Nilsen
  • Patent number: 10824364
    Abstract: In one embodiment, a local copy target is also a local primary of an incomplete consistency group of an ongoing asynchronous mirror relationship. Completion of the consistency group is facilitated notwithstanding that the local copy operation was initiated after the consistency group was initiated. In one aspect, asynchronous data mirroring logic, prior to the overwriting of existing data of the target, reads the existing data of the target for purposes of mirroring the read data to a remote secondary target of the consistency group. As a result, existing data of the local copy target which is also a local primary source of the consistency group, may be safely overwritten. Other features and aspects may be realized, depending upon the particular application.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: November 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Theresa M. Brown, Anthony J. Ciaravella, Nicolas M. Clayton, Michael S. Gagner, Theodore T. Harris, Jr., Mark L. Lipets, Gregory E. McBride, Carol S. Mellgren, Matthew J. Ward
  • Patent number: 10824570
    Abstract: A first memory stores a translation table indicating a first correspondence between a logical address and a physical address at first timing. A second memory stores a difference table that is configured to record, in each of entries, a correspondence between a logical address range and a physical address range, the correspondence representing a difference between the first correspondence and a second correspondence. The second correspondence is between the logical address and the physical address at second timing. In non-volatilizing data in a first logical address range to a first physical address range, in a case where the entries includes a first entry containing a correspondence between a second logical address range and a second physical address range, the controller updates the first entry. The first logical address range follows the second logical address range, and the first physical address range follows the second physical address range.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: November 3, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Satoshi Kaburaki, Tetsuhiko Azuma
  • Patent number: 10817201
    Abstract: Examples of a multi-level memory with direct access are described. Examples include designating an amount of a non-volatile random access memory (NVRAM) for use as memory for a computer system. Examples also include designating a second amount of the NVRAM to for use as storage for the computing device. Examples also include re-designating at least a first portion of the first amount of NVRAM from use as memory to use as storage.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: October 27, 2020
    Assignee: Intel Corporation
    Inventors: Blaise Fanning, Shekoufeh Qawami, Raymond S. Tetrick, Frank T. Hady