Abstract: A first controller manages first mapping information for accessing data stored in a storage area, management of which is assigned to the first controller, and second mapping information for accessing data stored in a predetermined storage area, management of which is assigned to a second controller. The second controller, when having executed garbage collection on the predetermined storage area, changes mapping information to post-migration mapping information for accessing data after being migrated by the garbage collection.

Abstract: Disclosed is a self-deploying encrypted hard disk, a deployment method thereof, a system and a boot method thereof.

Abstract: The present disclosure generally relates to writing data to streams. A host device can instruct a data storage device to operate in implied streams mode such that the host device does not need to tell the data storage device the specific stream in which to write data. The data storage device would maintain a list of open append points of specific streams. Upon receiving a write command, the data storage device determines whether the write command is for an already open stream, and if so, write to the specific stream. If not, then the data storage device opens a new stream or write the data to an overflow stream.

Abstract: Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

Abstract: Garbage collection or other computational work accesses memory which is located outside processor registers. Some embodiments specify at least some of the memory accesses and separate them from other computations, and utilize a memory access state machine to control the execution of both kinds of computation. Code that employs memory access results is placed in a run routine which is divided between respective states of the state machine. The specified memory accesses are invoked from a state code, and overlap other computation. A prefetch buffer may be dynamically sized based on the availability of space in the prefetch buffer. Code for shared work, such as address relocation code, may be placed in its own state structure. Candidate code for possible separation into a specified memory access routine may be automatically recognized.

Abstract: A storage system and related method are for operating solid-state storage memory in a storage system. Zones of solid-state storage memory are provided. Each zone includes a portion of the solid-state storage memory. The zone has a data write requirement for the zone for reliability of data reads. The storage system adjusts power loss protection for at least one zone. The adjusting is based on the data write requirement for the zone and responsive to detecting a power loss.

Abstract: Embodiments of the present disclosure relate to a method, an electronic device, and a computer program product for recommending a protection strategy. The method includes obtaining contents of attributes of a plurality of data assets adjusted. The method further includes generating a plurality of vector representations for the plurality of data assets based on the contents of the attributes. The method further includes dividing the plurality of data assets into at least one category based on the plurality of vector representations. The method further includes if it is determined that a protection strategy for one data asset in the at least one category exists, determining the protection strategy as a recommended strategy for another data asset in the at least one category.

Abstract: A computer system including one or more processors and persistent, word-addressable memory implements a persistent atomic multi-word compare-and-swap operation. On entry, a list of persistent memory locations of words to be updated, respective expected current values contained the persistent memory locations and respective new values to write to the persistent memory locations are provided. The operation atomically performs the process of comparing the existing contents of the persistent memory locations to the respective current values and, should they match, updating the persistent memory locations with the new values and returning a successful status. Should any of the contents of the persistent memory locations not match a respective current value, the operation returns a failed status. The operation is performed such that the system can recover from any failure or interruption by restoring the list of persistent memory locations.

Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

Abstract: Methods, systems, and devices for atomic write operations are described. A host system may receive a sequence of data that includes a first set of data and a second set of data. The host system may determine, based on the sequence of data, a first set of contiguous logical addresses for the first set of data and a second set of contiguous logical address for the second set of data. The host system may then transmit to a memory system a write command that indicates the first set of contiguous logical addresses and the second set of contiguous logical addresses. The first set of contiguous logical addresses may be discontiguous with the second set of contiguous logical addresses.

Abstract: Circuitry comprises memory access circuitry to control memory access by mapping virtual memory addresses in a virtual memory address space to physical memory addresses in a physical memory address space, the memory access circuitry being configured to provide a sparse mapping in which a mapped subset of the virtual memory address space is mapped to physical memory while an unmapped subset of the virtual memory address space is unmapped, the memory access circuitry being configured to discard write operations to virtual memory addresses in the unmapped subset of the virtual memory address space and processing circuitry to execute program code defining a processing operation to generate processed data and to store the processed data in a memory region of the virtual memory address space applicable to that processing operation; detector circuitry to detect whether the memory region is entirely within the unmapped subset of the virtual memory address space.

Abstract: An apparatus and method are provided for receiving a request from a plurality of processing units, where multiple of those processing units have associated cache storage. A snoop unit is used to implement a cache coherency protocol when a request is received that identifies a cacheable memory address. The snoop unit has snoop filter storage comprising a plurality of snoop filter tables organized in a hierarchical arrangement. The snoop filter tables comprise a primary snoop filter table at a highest level in the hierarchy, and each snoop filter table at a lower level in the hierarchy forms a backup snoop filter table for an adjacent snoop filter table at a higher level in the hierarchy. Each snoop filter table is arranged as a multi-way set associative storage structure, and each backup snoop filter table has a different number of sets than are provided in the adjacent snoop filter table.

Abstract: A first flag is set on a backup file to which data to be backed up is written. The first flag indicates that the backup file should be automatically retention locked after a cooling off period is over. Before the cooling off period is over, a request is received to open the backup file for writes. The request is allowed and upon allowing the request, the first flag is cleared and a second flag is set on the backup file indicating that writes are in progress. The clearing of the first flag excludes the backup file from being automatically retention locked after the cooling off period is over.

Abstract: A storage device includes a controller configured to receive a pre-processing instruction command from an external device, a non-volatile memory configured to store an original graph data, and a buffer memory connected to the controller and the non-volatile memory, wherein the controller is configured to load the original graph data from the non-volatile memory, generate pre-processing graph data by classifying the original graph data depending on vector similarity in response to the pre-processing instruction command, generate metadata on the basis of the pre-processing graph data, and provide the pre-processing graph data and the metadata to the non-volatile memory, the non-volatile memory is configured to store the pre-processing graph data and the metadata in a data block, and the buffer memory is configured to buffer the original graph data, the pre-processing graph data, and the metadata.

Abstract: A request is received to perform a multi-plane operation for data residing on a first plane and a second plane of a memory device. A first set of trim values is obtained from a first set of registers of the memory device. The first set of trim values corresponds to a first voltage shift for the data at the first plane. A second set of trim values is obtained from a second set of registers of the memory device. The second set of trim values corresponds to a second voltage shift for the data at the second set of trim values for the data at the second plane. The multi-plane operation is performed using at least the first set of trim values for the data at the first plane and at least the second set of trim values for the data at the second plane.

Abstract: A memory system may comprise: a memory device including a plurality of memory dies; and a controller including a first memory, Wherein the controller may store data segments of user data, corresponding to a plurality of commands received from a host, in the first memory, controls the memory device to sequentially store the data segments in the memory dies through interleaving, may update map segments of map data corresponding to storage of the data segments in the memory dies, may store the map segments in the first memory, controls the memory device to store the map segments stored in the first memory in the memory dies, and may assist the host in storing the map segments, stored in the first memory, in a second memory in the host.

Abstract: Control method and electronic device are provided. The electronic device includes: a controller; a first memory, connected to the controller and storing at least a boot system; and a second memory, connected to the controller, for storing update data of the boot system. After the electronic device completes a power-on self-test, the controller controls the first memory to be in an inaccessible state and controls the second memory to be in an accessible state.

Abstract: A determination can be made of a type of memory access workload for an application. A determination can be made whether the memory access workload for the application is associated with sequential read operations. The data associated with the application can be stored at one of a cache of a first type or another cache of a second type based on the determination of whether the memory workload for the application is associated with sequential read operations.

Abstract: Coordinated snapshots among storage systems implementing a promotion/demotion model, including monitoring a set of two or more target storage systems, wherein the two or more target storage systems are replication targets for respective portions of a source dataset; associating a first coordinated tracking dataset with two or more local tracking datasets maintained on the two or more target storage systems, wherein each local tracking dataset is a tracking copy for one portion of the source dataset; and advancing, in dependence upon a first coordinated target checkpoint, the first coordinated tracking dataset.

Abstract: A computer comprising one or more processors and memory may implement multiple threads that perform a lock operation using a data structure comprising an allocation field and a grant field. Upon entry to a lock operation, a thread allocates a ticket by atomically copying a ticket value contained in the allocation field and incrementing the allocation field. The thread compares the allocated ticket to the grant field. If they are unequal, the thread determines a number of waiting threads. If the number is above the threshold, the thread enters a long term wait operation comprising determining a location for long term wait value and waiting on changes to that value. If the number is below the threshold or the long term wait operation is complete, the thread waits for the grant value to equal the ticket to indicate that the lock is allocated.