Abstract: Method and apparatus for trimming IC components. In an embodiment, a circuit includes a digital controller, a first programmable read only memory coupled to the controller, and a trimmable block having at least one trimmable component. A second programmable read only memory is coupled to the trimmable block, where the second programmable read only memory is independent of the first programmable read only memory.

Abstract: Techniques are provided for mapping storage objects to storage controllers using digital twins. One method comprises obtaining a virtual representation of a storage system that comprises storage objects and storage controllers, wherein a given storage object is mapped to a particular storage controller according to a storage object to storage controller mapping configuration; configuring the virtual representation of the storage system, for multiple iterations, based on at least one storage metric for respective storage objects, wherein each iteration corresponds to a different storage object to storage controller mapping configuration and generates a load balance score for the respective storage object to storage controller mapping configuration; selecting a given storage object to storage controller mapping configuration based on the respective load balance scores; and initiating an implementation of the selected storage object to storage controller mapping configuration in the storage system.

Abstract: Systems and methods are disclosed for providing host-independent data operations. In certain embodiments, a data storage device includes a non-volatile memory; a pinhole button configured to be pressed; and a controller configured to: detect that the pinhole button is pressed; detect that the data storage device is coupled to a direct-current (DC) power supply; and initiate a disk operation for the data storage device. In some embodiments, the controller can be configured to initiate a data operation, such as an authentication or data accessibility operation, a data security operation, etc., for example, in addition to or instead of a disk operation.

Abstract: The present disclosure provides a resource object processing method, a device, and a storage medium. The method includes: obtaining a control unit identifier set and a service address set of a federated storage cluster control layer, the control unit identifier set being used to maintain respective unit identifiers of multiple control units independent and isolated, and supported in the federated storage cluster control layer; mapping a unit identifier of a target control unit uniquely corresponding to the target object from the control unit identifier set according to a first object identifier of a target object to be processed; and determining a target service address corresponding to the target control unit from the service address set according to the unit identifier of the target control unit, establishing a communication connection based on the target service address, and performing a resource processing operation of the target object through the communication connection.

Abstract: Techniques described herein relate to a method for performing generating backups of host data. The method may include obtaining a backup request associated with an asset of the host; obtaining file system metadata associated with the asset from a file system metadata repository; identifying data in a disk of the host associated with the asset based the file system metadata; obtaining file size and cluster size associated with each file of a file system using the file system metadata; making a determination that the actual size and cluster size do not match for at least one file of files of a file system; identifying a difference between the actual size and the cluster size of the at least one file of files; identifying the difference as slacks; generating slack metadata associated with the slacks; and providing slack data and the slack metadata to post processing engines.

Abstract: According to one embodiment, a memory device includes a controller, a nonvolatile memory, and a cache memory. The controller is configured to record a plurality of first addresses sequentially accessed to read data stored in the nonvolatile memory, acquire an address list including a second address within the first addresses and a third address within the first addresses which is estimated to be accessed after the second address is accessed, read data from the nonvolatile memory based on the third address included in the address list if the second address included in the address list is accessed, and store, in the cache memory, the data read from the nonvolatile memory.

Abstract: A memory request issue counter (MRIC) is maintained that is incremented for every memory access a central processing unit core makes. A region reuse distance table is also maintained that includes multiple entries each of which stores the region reuse distance for a corresponding region. When a memory access request for a physical address is received, a reuse distance for the physical address is calculated. This reuse distance is the difference between the current MRIC value and a previous MRIC value for the physical address. The previous MRIC value for the physical address is the MRIC value the MRIC had when a memory access request for the physical address was last received. A region reuse distance for a region that includes the physical address is generated based on the reuse distance for the physical address and used to manage the cache.

Abstract: The present disclosure relates generally to techniques for processing asynchronous queries across multiple data cores including secondary data cores stored in the secondary storage system in a distributed computing system. Data from secondary data cores are recovered to new data cores generated in the data plane in order to be accessible for searching. Using this technique, asynchronous queries are run in parallel allowing the client to dynamically manage the queries and receive notifications when results are available.

Abstract: Systems and methods for orchestrating coordinated snapshots across distinct storage environments are disclosed. The methods include steps for determining, for storage systems storing portions of a dataset, that a local checkpoint at a storage system of the storage systems meets dependency requirements for a coordinated checkpoint of the dataset relative to another local checkpoint at another storage system of the storage systems while storage operations are being applied to the dataset, and based on the determination, orchestrating the coordinated checkpoint.

Abstract: A method for restoring data and a non-volatile memory performing the restore operation are disclosed. If a restore command is applied, an internal read command is generated to sequentially designate the addresses. A read operation is performed on the designated address, and the number of error bits in a code word is compared with a reference number of error bits. Depending on the result of the comparison, an update or restore operation on a corrected code word for the designated address is selectively performed.

Abstract: A switching controller controlling communication between a processor included in an external device and a memory included in a storage device may pre-fetch memory data into a buffer memory inside the switching controller and provides the data to the processor of the external device based on a command input for a predetermined period.

Abstract: A method for garbage collection includes obtaining a request to perform garbage collection on a target table. The target table includes a plurality of pages. The method includes determining, based on the request, a garbage collection transaction identifier (ID) specifying a global minimum transaction ID for garbage collection. For each respective page of a first set of pages of the plurality of pages, the method includes retrieving, from a page transaction ID table, a respective page minimum transaction ID corresponding to the respective page. The page transaction ID table is different from the target table. The method also includes determining that the respective page minimum transaction ID is greater than the global minimum transaction ID and, based on determining that the respective page minimum transaction ID is greater than the global minimum transaction ID, skipping garbage collection of the respective page without accessing the respective page.

Abstract: A computing device having a computer express link (CXL) connection between a memory sub-system and a host system and having storage access queues configured at least in part in the memory sub-system. The memory sub-system can attach, as a memory device, a portion of its fast random access memory over the connection to the host system. One or more storage access queues can be configured in the memory device. The host system can use a cache-coherent memory access protocol to communicate storage access messages over the connection to the random access memory of the memory sub-system. Optionally, the host system can have a memory with second storage access queues usable to access the storage services of the memory sub-system over the connection using a storage access protocol.

Abstract: A system includes a memory device having a plurality of blocks. A first subset of the plurality of blocks is configured as single-level cell (SLC) memory and a second subset of the plurality of blocks is configured as multi-level cell (MLC) memory. A processing device, operatively coupled to the memory device, determines that a first block of a set of blocks of the first subset is a bad block, wherein the first block is located in a first plane of the memory device. The processing device converts a second block of the set of blocks to the MLC memory of the second subset, wherein the second block is located in a second plane of the memory device, and wherein the second plane is neighboring the first plane.

Abstract: Provided is a method for managing an adaptive cache pool, which is performed by one or more processors, and includes receiving monitoring information on a cache memory divided into a plurality of cache pools, and adjusting a cache region associated with at least one of the plurality of cache pools based on the monitoring information.

Abstract: Various illustrative aspects are directed to a data storage device, method, and one or more processing devices that are configured to: select a seek time model from a plurality of seek time models based at least in part on an operational characteristic of an access command, the operational characteristic relating to an off-track susceptibility of executing the access command; determine an access time for the access command using the selected seek time model; and select a next access command for execution based on the determined access time for the access command and determined access times for other ones of a plurality of access commands.

Abstract: This disclosure provides systems, methods, and devices for memory systems that support enhanced write buffer flush schemes. In a first aspect, a method performed by a memory controller includes detecting, by the memory controller, a flush operation associated with a write buffer. The method also includes detecting, by the memory controller during the flush operation, a command for placement into a command queue. The method further include prioritizing, by the memory controller, the flush operation to by placing the command in a wait queue and maintaining the flush operation. Other aspects and features are also claimed and described.

Abstract: This disclosure provides a method and an apparatus for accessing a solid state disk (SSD). The method is applied to a storage node, the storage node includes a network interface card and an SSD, and the network interface card includes a memory. The network interface card receives a data write request sent by a client, where the data write request includes to-be-written data. The network interface card writes the to-be-written data to the memory of the network interface card, and the SSD obtains the to-be-written data from the memory of the network interface card and writes the to-be-written data to the SSD.

Abstract: A method for programming a memory device having a plurality of planes is provided. Program commands and addresses are received. Each of the addresses associated with one of the program commands. A first plane of the plurality of planes are determined according to a first address of the addresses. A page register of the first plane is reset. A second plane of the plurality of planes is determined according to a second address of the addresses. A page register of the second plane is reset.

Abstract: Examples described herein relate to programming a memory rule for a home agent, wherein the programming a memory rule for a home agent comprises: receiving at least one memory rule programming and based on a cluster associated with the home agent, configuring a memory rule register using a memory rule programming from among the at least one memory rule programming. In some examples, receiving at least one memory rule programming includes receiving a first memory rule programming and receiving a second memory rule programming. In some examples, a mask is applied to reject the first memory rule programming; and applying the mask to accept the second memory rule programming and program the memory rule for the home agent.