Abstract: An integrated circuit package is presented. In an embodiment, the integrated circuit package has contact pads formed on the top side of a package substrate, a die electrically attached to the contact pads, and input/output (I/O) pads formed on the top side of the package substrate. The I/O pads are electrically connected to the contact pads. The integrated circuit package also includes a flex cable receptacle electrically connected to the I/O pads on the top side of the package substrate. The flex cable receptacle is non-compressively attachable to a flex cable connector and includes receptacle connection pins electrically connected to the I/O pads.

Abstract: A display panel including an array substrate and a COF substrate is provided. The COF is provided with a plurality of welded lead lines. The array substrate includes a metal layer disposed on a surface of the substrate, a silicon nitride layer disposed on a surface of the metal layer, and a plurality of terminal wires disposed in a spaced arrangement in a welding region on a surface of the second silicon nitride layer. The welding region between the adjacent terminal wires is provided with through holes, which expose the metal layer. The risk of corrosion and breakage of the welded lead lines on the COF substrate is effectively reduced.

Abstract: A semiconductor device includes a cooling device, an insulating substrate, a semiconductor element, an external connection terminal, and a resin portion. The insulating substrate is brazed to an outer surface of the cooling device. The semiconductor element is brazed to the insulating substrate. The external connection terminal includes a first end, which is electrically connected to the semiconductor element, and an opposite second end. The resin portion is molded to the insulating substrate, the semiconductor element, the first end of the external connection terminal, and at least part of the cooling device.

Abstract: A method for producing at least one pad assembly (32, 50) on a support (19, 43) for use in a method for self-assembling at least one element (10) on the support (19, 43), comprises fanning, on the support (19, 43), a layer (28, 48) of at least one fluorinated material around the location (30, 44) of the pad assembly (32, 50), the layer (28, 48) having a thickness greater than 10 nm. The layer (28, 48) and the location (30, 44) are exposed to an ultraviolet treatment in the presence of ozone to form the pad assembly (32, 50) at said location (30, 44), wherein a drop of liquid (16) having a static contact angle on the pad assembly (32, 50) less than or equal to 15°, after the exposure to the ultraviolet treatment, has a static contact angle on the layer (28, 48) greater than or equal to 100°.

Abstract: Technique capable of achieving reliability improvement of a semiconductor device even if temperature rising of an operation guarantee temperature of the semiconductor device is performed is provided. Gap portions are provided among a plurality of pads, and a glass coat composed of, for example, a silicon oxide film or a silicon nitride film is embedded in the gap portions. The glass coat is provided in order to secure electrical insulation among the pads, and coats outer edge portions of the pads. Trenches are formed so as to be adjacent to regions, which are coated with the glass coat, of the outer edge portions of the pads.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. A carrier is removed after a first semiconductor die and a second semiconductor die are stacked on each other, and then a first encapsulant is formed, so that the carrier may be easily removed when compared to approaches in which a carrier is removed from a wafer having a thin thickness.

Abstract: Various embodiments of an integrated device package are disclosed herein. The package may include a leadframe having a first side and a second side opposite the first side. The leadframe can include a plurality of leads surrounding a die mounting region. A first package lid may be mounted on the first side of the leadframe to form a first cavity, and a first integrated device die may be mounted on the first side of the leadframe within the first cavity. A second integrated device die can be mounted on the second side of the leadframe. At least one lead of the plurality of leads can provide electrical communication between the first integrated device die and the second integrated device die.

Abstract: Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

Abstract: In one implementation, a power semiconductor package includes a conductive carrier including a switch node segment and a power output segment. The power semiconductor package also includes an integrated output inductor stacked over the conductive carrier and configured to couple the switch node segment to the power output segment. The power semiconductor package further includes a power stage stacked over the integrated output inductor, the power stage including a pulse-width modulation (PWM) control and driver coupled to a control transistor and a sync transistor.

Abstract: A method of making a micro-wire rib structure includes providing a substrate and locating a curable layer on or over the substrate. The curable layer is imprinted and cured to form a cured layer including a cured-layer surface and a micro-channel having a micro-channel depth, a micro-channel bottom, first and second micro-channel sides, and one or more ribs having opposing rib sides and a rib top defining a rib height less than the micro-channel depth. Each rib is located between the first and second micro-channel sides and extends from the micro-channel bottom toward the cured-layer surface. A curable conductive material is located in the micro-channel and cured to provide a cured electrical conductor forming a micro-wire in the micro-channel.

Abstract: A circuit assembly is disclosed which includes first and second substrates disposed on a heat dissipation base, and first and second semiconductor elements mounted on the first and second substrates. The first and second substrates are wired together, and three main electrode terminals are provided when the first and second semiconductor elements are connected in series, while two main electrode terminals are provided when the first and second semiconductor element are connected in parallel. In both cases, the circuit assembly is covered with a common exterior case so that one portion of each main electrode terminal or one portion of each main electrode terminal is exposed. Parts used in the circuit assembly are shared, and by changing the wiring between the first and second substrates, semiconductor modules with different functions are realized at low cost.

Abstract: A method for forming a metal bump is provided. Firstly, a photo-resist layer is formed on an IC chip by using a lithographic process. The photo-resist layer comprises a metal bump reserved groove and a metal bump slit reserved portion with the extent covering a metal pad. The metal bump slit reserved portion is formed on the metal pad and within the metal bump reserved groove. Then, a deposition process is applied to form the metal bump in the metal bump reserved groove and have the metal bump slit reserved portion penetrating the metal bump. Afterward, the photo-resist layer is removed to leave the metal bump with a metal bump slit therein.

Abstract: Provided is a method of manufacturing a semiconductor device that has a plurality of semiconductor components and a plurality of resin layers, the method including: a step in which resin layers and semiconductor components are laminated alternately on a substrate, and the same is adhered by being subjected to heating and pressurization at a temperature lower than the temperature at which the substrate and/or a solder layer of the semiconductor components melts; and a step in which heat and pressure are applied at a temperature at which the solder layer melts or a temperature higher than said temperature.

Abstract: A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the device die, wherein the die-attach film is attached to the device die. A plurality of redistribution lines includes portions level with the die-attach film. A plurality of Z-interconnects is electronically coupled to the device die and the plurality of redistribution lines. A polymer-comprising material is under the inter-layer dielectric. The device die, the die-attach film, and the plurality of Z-interconnects are disposed in the polymer-comprising material.

Abstract: Disclosed herein are a semiconductor package and a method of manufacturing the same, the semiconductor package including: a molding member having a cavity formed therein; a device mounted in the cavity; an insulating member formed inside the cavity and on and/or beneath the molding member and the device; a circuit layer formed on the insulating member, and including vias and connection pads electrically connected with the device; a solder resist layer formed on the circuit layer, and having openings exposing upper portions of the connection pads; and solder balls formed in the openings.

Abstract: Technique capable of achieving reliability improvement of a semiconductor device even if temperature rising of an operation guarantee temperature of the semiconductor device is performed is provided. Gap portions are provided among a plurality of pads, and a glass coat composed of, for example, a silicon oxide film or a silicon nitride film is embedded in the gap portions. The glass coat is provided in order to secure electrical insulation among the pads, and coats outer edge portions of the pads. Trenches are formed so as to be adjacent to regions, which are coated with the glass coat, of the outer edge portions of the pads.

Abstract: A semiconductor device has a semiconductor die with composite bump structures over a surface of the semiconductor die. A conductive layer is formed over a substrate. A patterning layer is formed over the substrate. A first portion of the patterning layer is removed to form an opening to expose the substrate and conductive layer. A second portion of the patterning layer is removed to form a sloped surface in the patterning layer extending from a surface of the patterning layer down to the substrate. The sloped surface in the patterning layer can be linear, concave, or convex. The die is mounted to the substrate with the composite bump structures electrically connected to the conductive layer. An underfill material is deposited over the surface of the patterning layer. The sloped surface in the patterning layer aids with the flow of underfill material to cover an area between the die and substrate.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead; placing an integrated circuit device, having an external connector, adjacent to and electrically isolated from the lead; mounting an integrated circuit over the lead and the integrated circuit device with the integrated circuit electrically isolated from the integrated circuit device; and forming a package encapsulation, having an encapsulation base, over the lead, the integrated circuit, and the integrated circuit device with the lead and the external connector exposed from the encapsulation base.

Abstract: A semiconductor package device includes a lower package including a lower semiconductor chip mounted on the lower package substrate, a lower molding compound layer disposed on the lower package substrate, a first trench formed in the lower molding compound layer to surround the lower semiconductor chip, and a second trench connected to the first trench to extend to an outer wall of the lower package, the second trench being formed in the lower molding compound layer, an upper package disposed on the lower package. The upper package includes an upper package substrate and at least one upper semiconductor chip mounted on the upper package substrate and a heat transfer member disposed between the lower package and the upper package.

Abstract: An interconnection device for elements to be interconnected such as electronic modules or circuits, comprises at least one transmission line coupled to a ground line, the two lines being produced on a face of a dielectric substrate, the interconnection being made substantially at the ends of the transmission line and of the ground line, wherein said interconnection device is flexible over at least a part of its length situated roughly between the elements to be interconnected.