Patents Examined by Sheila V. Clark
  • Patent number: 8232630
    Abstract: Even when a mold part of an IC module is exposed from an opening provided in a substrate of an inlay, occurrence of malfunction, communication disorders or the like of the IC module due to the influence of an external impact or the like is prevented. By combining a sealing member including an insulating layer and an adhesive layer in a stacked manner to a shape covering a mold part of the IC module, occurrence of malfunction, communication disorders or the like of the IC module is prevented even if there is an influence of an external impact or the like. Meanwhile, by providing a sealing member, concentration of stress on the mold part in a line pressure test is alleviated by limiting the size of the sealing member, and also occurrence of cracks in the mold part can be prevented.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: July 31, 2012
    Assignee: Toppan Printing Co., Ltd.
    Inventors: Yutaka Ohira, Chiaki Ishioka
  • Patent number: 8222719
    Abstract: A QFN IC package is provided that has all of the advantages of the typical QFN IC package, but in addition, has a paddle that is configured to facilitate trace routing and/or via placement on the PWB or PCB on which the IC package is mounted. By configuring the paddle as necessary or desired in order to facilitate routing and/or via placement, the overall size of the PWB or PCB can be reduced without sacrificing the thermal or electrical performance advantages that the paddle provides. In addition, the reduction in the overall size of the PWB or PCB results in reduced cost.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: July 17, 2012
    Assignee: Agere Systems, Inc.
    Inventors: Lawrence Wayne Golick, Scott E. Hynes, Thomas J. Pllyer
  • Patent number: 8222740
    Abstract: A transparent, electrically conductive composite includes a layer of molybdenum oxide or nickel oxide deposited on a layer of zinc oxide layer. The molybdenum component exists in a mixed valence state in the molybdenum oxide. The nickel component exists in a mixed valence state in the nickel oxide. The composite may be utilized in various electronic devices, including optoelectronic devices. In particular, the composite may be utilized as a transparent conductive electrode. As compared to conventional transparent conduct oxides such as indium tin oxide, the composite exhibits superior properties, including a higher work function.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: July 17, 2012
    Inventor: Jagdish Narayan
  • Patent number: 8215900
    Abstract: A turbine vane assembly includes an airfoil extending between an inner shroud and an outer shroud. The airfoil can include a substructure having an outer peripheral surface. At least a portion of the outer peripheral surface is covered by an external skin. The external skin can be made of a high temperature capable material, such as oxide dispersion strengthened alloys, intermetallic alloys, ceramic matrix composites or refractory alloys. The external skin can be formed, and the airfoil can be subsequently bi-cast around or onto the skin. The skin and the substructure can be attached by a plurality of attachment members extending between the skin and the substructure. The skin can be spaced from the outer peripheral surface of the substructure such that a cavity is formed therebetween. Coolant can be supplied to the cavity. Skins can also be applied to the gas path faces of the inner and outer shrouds.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: July 10, 2012
    Assignee: Siemens Energy, Inc.
    Inventor: Jay A. Morrison
  • Patent number: 8217503
    Abstract: A package structure for DC-DC converter disclosed herein can reduce the number of encapsulated elements as a low-side MOSFET chip can be stacked above the high-side MOSFET chip of a first die pad, through die pads of different thicknesses or interposers with joint parts of different thicknesses; moreover, it further reduces the size of the entire semiconductor package as a number of bond wires are contained in the space between the controller and the low-side MOSFET chip. Moreover, electrical connection between the top source electrode pin and the bottom source electrode pin of the low-side MOSFET chip is realized with a metal joint plate, such that when the DC-DC converter is sealed with plastic, the metal joint plate can be exposed outside to improve the thermal performance and effectively reduce the thickness of the semiconductor package.
    Type: Grant
    Filed: September 14, 2010
    Date of Patent: July 10, 2012
    Assignee: Alpha & Omega Semiconductor Inc.
    Inventors: Yueh-Se Ho, Yan Xun Xue, Jun Lu
  • Patent number: 8212368
    Abstract: A semiconductor package, a manufacturing method thereof and an encapsulating method thereof are provided. The semiconductor package includes a substrate, a semiconductor chip, a plurality of conductive parts and a sealant. The conductive parts electrically connect an upper surface of the substrate and an active surface of the semiconductor chip. The sealant covers a back surface of the semiconductor chip, wherein the space between the upper surface of the substrate and the active surface of the semiconductor chip is filled with a portion of the sealant. The back surface of the semiconductor is spaced apart from a top surface of the sealant by a first distance, the upper surface of the substrate is spaced apart from the active surface of the semiconductor chip by a second distance, and the ratio of the first distance to the second distance is smaller than or equal to 5.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: July 3, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chung-Yao Kao, Tsang-Hung Ou
  • Patent number: 8212350
    Abstract: In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: July 3, 2012
    Assignee: Intel Corporation
    Inventors: Mark B. Trobough, Christopher S. Baldwin
  • Patent number: 8207618
    Abstract: This semiconductor device is a semiconductor device in which a semiconductor element is flip-chip mounted onto a circuit substrate and the semiconductor element is covered and sealed with a sealing resin. A recess portion is formed in the sealing resin on a surface opposite to the mounting surface of the semiconductor element. Warping of the semiconductor device is reduced by the action of this recess portion.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: June 26, 2012
    Assignee: Panasonic Corporation
    Inventors: Kazumichi Shimizu, Yoshihiro Tomura, Masahiro Ono
  • Patent number: 8202238
    Abstract: A thin film integrated circuit which is mass produced at low cost and a method for manufacturing a thin film integrated circuit according to the invention includes the steps of: forming a peel-off layer over a substrate; forming a base film over the peel-off layer; forming a plurality of thin film integrated circuits over the base film; forming a groove at the boundary between the plurality of thin film integrated circuits; and introducing a gas or a liquid containing halogen fluoride into the groove, thereby removing the peel-off layer; thus, the plurality of thin film integrated circuits are separated from each other.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: June 19, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Miho Komori, Yurika Satou, Kazue Hosoki, Kaori Ogita
  • Patent number: 8193086
    Abstract: Electromigration behavior in complex metallization systems of semiconductor devices may be enhanced at critical areas between a metal line and a via by locally forming a copper/silicon compound. In some illustrative embodiments, the formation of the copper/silicon compound may be combined with other treatments for cleaning the exposed surface areas and/or modifying the molecular structure thereof.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: June 5, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Tobias Letz, Frank Feustel
  • Patent number: 8174122
    Abstract: A trench is formed in an insulation film formed on top of a semiconductor substrate, and a barrier metal film is formed on the surface of the trench. After a copper or copper alloy film is formed on the barrier metal film, an oxygen absorption film in which a standard energy of formation of an oxidation reaction in a range from room temperature to 400° C. is negative, and in which an absolute value of the standard energy of formation is larger than that of the barrier metal film is formed, and the assembly is heated in a temperature range of 200 to 400° C. A semiconductor device can thereby be provided that has highly reliable wiring, in which the adhesion to the barrier metal film in the copper interface is enhanced, copper diffusion in the interface is suppressed, and electromigration and stress migration are prevented.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: May 8, 2012
    Assignee: NEC Corporation
    Inventors: Mari Amano, Munehiro Tada, Naoya Furutake, Yoshihiro Hayashi
  • Patent number: 8174029
    Abstract: The purpose of the invention is to improve reliability of a light emitting apparatus comprising TFTs and organic light emitting elements.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: May 8, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Murakami, Masayuki Sakakura, Toru Takayama
  • Patent number: 8169085
    Abstract: A semiconductor device according to one embodiment includes: a substrate; a wiring provided above the substrate and including a graphene nanoribbon layer comprising a plurality of laminated graphene nanoribbon sheets; and a wiring connecting member penetrating at least one of the plurality of graphene nanoribbon sheets for connecting the wiring and a conductive member above or below the wiring.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: May 1, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yousuke Akimoto, Makoto Wada
  • Patent number: 8162595
    Abstract: One embodiment provides a system that mitigates vibrations caused by cooling fans in a computer system. More specifically, the system includes a cooling fan mechanically coupled to the chassis of the computer system, wherein vibrations generated by the cooling fan are coupled to the chassis. The system also includes an actuation mechanism that creates a relative displacement between the cooling fan and the chassis when a control signal is applied to the actuation mechanism. The system additionally includes a detection mechanism which detects the relative displacement and generates a feedback signal which represents the relative displacement. The system further includes a control signal generation mechanism which converts the feedback signal into the control signal, which is subsequently applied to the actuation mechanism. When the control signal is applied to the actuation mechanism, the relative displacement between the cooling fan and the chassis vibrationally decouples the cooling fan from the chassis.
    Type: Grant
    Filed: May 5, 2009
    Date of Patent: April 24, 2012
    Assignee: Oracle America, Inc.
    Inventors: Steven F. Zwinger, Kenny C. Gross, Aleksey M. Urmanov
  • Patent number: 8159060
    Abstract: Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. The patterns of the metal pads and bondable dielectric material portions in the first and second substrates can have a mirror symmetry. The first and second substrates are brought into physical contact and bonded employing contacts between metal pads and contacts between the bondable dielectric material portions. Through-substrate-via (TSV) structures are formed through bonded dielectric material portions. The interface between each pair of bonded dielectric material portions located around a TSV structure is encapsulated by two diffusion resistant dielectric material layers so that diffusion of metal at a bonding interface is contained within each pair of bonded dielectric material portions.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: April 17, 2012
    Assignee: International Business Machines Corporation
    Inventors: Karl W. Barth, Ricardo A. Donaton, Spyridon Galis, Kevin S. Petrarca, Shahab Siddiqui
  • Patent number: 8148812
    Abstract: A thermal resistor is a metal body having a contact surface to be partially in contact to form a void and is electrically conductive as a whole. The thermal body may be a layered body having a plurality of metal bodies layered so as to be partially in contact with one another to form a void between them, or a metal body having a plurality of convex and concave portions on the surface, or a metal body formed by a plurality of metal plates each having a plurality of creases and layered so that the creases of the adjacent metal plates intersect, or a layered metal body formed by metal plates each having elasticity in the thickness direction and having elasticity in the layered direction as a whole, or metal body having a film formed by a different metal. Also disclosed in a semiconductor device having the thermal resistor inserted between a heating semiconductor element and a case cover and between a heat spreader and the case cover. Also disclosed is an electric device using the device.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: April 3, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventor: Koji Kise
  • Patent number: 8138616
    Abstract: A bond pad structure of an integrated circuit includes a conductive pad disposed on a first dielectric layer, a first conductive block formed in a second dielectric layer below the first dielectric layer and electrically connected to the conductive pad through a first via plug formed in the first dielectric layer, and an electrically floating first conductive plate situated under the conductive pad.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: March 20, 2012
    Assignee: Mediatek Inc.
    Inventors: Tien-Chang Chang, Tao Cheng, Chien-Hui Chuang, Bo-Shih Huang
  • Patent number: 8128368
    Abstract: Apparatus for the ventilation of a rotor hub of a wind energy plant, with a cup-shaped ventilation cap, which has a circumferential side wall and a base portion, wherein the side wall has at least one bore for draining water and the base portion has at least one bore for ventilation, a pipe-shaped connection piece, which has an air entrance opening which runs out into an interior space of the rotor hub, wherein the ventilation cap is arranged before the air entrance opening and the at least one bore for ventilation is arranged in the ventilation cap outside of the air entrance opening of the pipe-shaped connection piece such that the air entrance opening is covered up by the ventilation cap.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: March 6, 2012
    Assignee: Nordex Energy GmbH
    Inventor: Lars Christian Bielefedt
  • Patent number: 8125068
    Abstract: A semiconductor chip including a chip via plug penetrating a substrate, a semiconductor stack thereof, a semiconductor device package thereof, and an electronic apparatus having the same are disclosed. The semiconductor chip comprising, a substrate including an inner semiconductor circuit, a conductive redistribution structure formed on the substrate including a conductive redistribution interconnection and a conductive redistribution via plug, wherein the redistribution via plug is connected to the inner semiconductor circuit; a conductive chip pad formed on the substrate, and a conductive chip via plug configured to penetrate the substrate and electrically connected to the redistribution structure.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: February 28, 2012
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventor: Jong-Joo Lee
  • Patent number: 8120163
    Abstract: A structure of a high frequency non-reciprocal passive device, such as circulator/isolator and method of installation. The structure includes a substantially rigid lip with cutouts for hot leads to go through. The walls of the cutout are situated in close proximity and symmetrically to the leads. The structure also having mounting holes. The installation process includes a step of putting the structure into a pocket in a carrier wherein a defined amount of a low heat transfer/electrical resistance substance, for example a grease, is located. The size of the lip is larger than the size of the pocket. Therefore the structure is supported on the rim of the pocket, while its portion which is under the lip and having smaller size is located in the pocket. Mounting screws can provide a predetermined pressure to the carrier by the device housing.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: February 21, 2012
    Assignee: Renaissance Electronics Corporation
    Inventor: Thampy Kurian