Abstract: Provided is a semiconductor package including a first substrate including a first substrate pad and a second substrate pad spaced apart from each other, first semiconductor chips stacked on the first substrate and having a first side surface and a second side surface, first chip pads disposed on the first substrate pad and adjacent to the first side surface and provided to the respective first semiconductor chips in the peripheral circuit region and electrically connected to the first substrate pad, and a second semiconductor chip disposed toward the second side surface and including a second chip pad spaced apart from the first chip pad and electrically connected to the second substrate pad, and a heat insulation member provided to the first substrate between the at least one first substrate pad and the at least one second substrate pad.

Abstract: A plurality of electrodes are electrically coupled to each other by conductive interconnects formed from selectively sintered nanoparticles.

Abstract: An integrated circuit (IC) includes a substrate having a top side having active circuitry thereon including a plurality of metal interconnect levels including a first metal interconnect level and a top metal interconnect level, and a bottom side. At least one TSV array includes a plurality of TSVs. The TSVs are positioned in rows including a plurality of interior rows and a pair of exterior rows and a plurality of columns including a plurality of interior columns and a pair of exterior columns. At least a portion of the TSVs in the array are electrically connected TSVs that are coupled to a TSV terminating metal interconnect level selected from the plurality of metal interconnect levels. At least one of the exterior rows or exterior columns include a lower number of electrically connected TSVs compared to a maximum number of electrically connected TSVs in the interior rows and interior columns, respectively.

Abstract: A method for axial thrust control of a gas turbine, and a gas turbine with a device for controlling axial thrust are provided. A gas turbine, with regard to aerodynamic forces and pressure forces, which exert an axial force upon the rotor, is configured such that at no-load and low partial load it has a negative thrust, and at high load it has a positive thrust. In order to ensure a resulting positive thrust upon the thrust bearing within the entire load range of the gas turbine, an additional thrust is applied in a controlled manner. The additional thrust for example can be controlled in dependence upon the gas turbine load. The resulting thrust force at full load is consequently less than in the case of a conventionally designed gas turbine without thrust balance.

Abstract: An enhanced redistribution layer is provided that geometrically expands redistribution layer (RDL) pads associated with a ball grid array of a wafer level package (WLP) to provide tensile stress relief during temperature cycle and/or drop testing of the WLP.

Abstract: A multi-tiered IC device contains a first die including a substrate with a first and second set of vias. The first set of vias extends from one side of the substrate, and the second set of vias extend from an opposite side of the substrate. Both sets of vias are coupled together. The first set of vias are physically smaller than the second set of vias. A second die having a set of interconnects is stacked relative to the first die in which the interconnects couple to the first set of vias.

Abstract: A steam turbine rotating blade for a low pressure section of a steam turbine engine is disclosed. The steam turbine rotating blade includes an airfoil portion. A root section is attached to one end of the airfoil portion. A dovetail section projects from the root section, wherein the dovetail section includes a skewed axial entry dovetail. A tip section is attached to the airfoil portion at an end opposite from the root section. A cover is integrally formed as part of the tip section. The cover comprises a first flat section, a second flat section, and a depression section located laterally between the first flat section and second flat section. The depression section is located below the first flat section at a first end where the first flat section and depression section are contiguous. The depression section rises above to the second flat section at a second end where the second flat section and depression section are contiguous. The second flat section is raised above the first flat section.

Abstract: A wafer level chip scale package having stud bumps and a method for fabricating the same are described. The wafer level chip scale package includes a silicon substrate having a passivation layer and a chip pad on its top surface; a stud bump being formed on the chip pad and encircled by a first insulating layer; a re-distributed line (RDL) pattern being formed on the same horizontal surface as the first insulating layer and the stud bump, the RDL pattern for connecting the stud bump and a solder bump; a second insulating layer for insulating the RDL pattern so that a portion of the RDL pattern that is connected with the solder bump is exposed; and the solder bump being attached to the exposed portion if the RDL pattern.

Abstract: Disclosed are embodiments of a semiconductor structure that incorporates multiple nitride layers stacked between the center region of a device and a blanket oxide layer. These nitride layers are more thermally conductive than the blanket oxide layer and, thus provide improved heat dissipation away from the device. Also disclosed are embodiments of a method of forming such a semiconductor structure in conjunction with the formation of any of the following nitride layers during standard processing of other devices: a nitride hardmask layer (OP layer), a “sacrificial” nitride layer (SMT layer), a tensile nitride layer (WN layer) and/or a compressive nitride layer (WP layer). Optionally, the embodiments also incorporate incomplete contacts that extend through the blanket oxide layer into one or more of the nitride layers without contacting the device in order to further improve heat dissipation.

Abstract: A steam turbine rotating blade for a low pressure section of a steam turbine engine is disclosed. The steam turbine rotating blade includes an airfoil portion. A root section is attached to one end of the airfoil portion. A dovetail section projects from the root section, wherein the dovetail section includes a straight axial entry dovetail. A tip section is attached to the airfoil portion at an end opposite from the root section. A cover is integrally formed as part of the tip section. The cover has a first portion that overhangs a pressure side of the airfoil portion and a second portion that overhangs a suction side of the airfoil portion. The cover is positioned at an angle relative to the tip section, wherein the angle ranges from about 15 degrees to about 35 degrees.

Abstract: Provided is an adhesive tape which adheres two members to each other and decreases problems that may occur due to contraction and expansion of the adhered members when the temperature of the adhered two members changes. The adhesive tape includes: a base film having insulating properties; and an adhesive agent that adheres on both sides of the base film, wherein a coefficient of thermal expansion of the base film is 10 ppm or lower, a coefficient of thermal expansion of the adhesive tape is lower than 17 ppm, and an occupation rate of the base film in the adhesive tape exceeds 50%.

Abstract: An enhanced redistribution layer is provided that geometrically expands redistribution layer (RDL) pads associated with a ball grid array of a wafer level package (WLP) to provide tensile stress relief during temperature cycle and/or drop testing of the WLP.

Abstract: A wiring structure of a semiconductor device or the like includes an interlayer insulating film having a fluorocarbon film formed on an underlayer, and a conductor buried in the interlayer insulating film. The fluorocarbon film contains nitrogen and is low in dielectric constant, excellent in reproducibility and stable.

Abstract: A semiconductor device includes a substrate, a die assembly attachable to the substrate and a flexible strip extending over the substrate and the die assembly. The flexible strip has one or more routing circuits carried thereon. The die assembly and the substrate are arranged to be electrically connected through the one or more routing circuits carried on the flexible strip.

Abstract: A semiconductor integrated circuit device includes a plurality of contact layers located between two lines running in parallel in a first direction. Each of the contact layers has a structure in which an upper contact and a lower contact are coupled together. The plurality of contact layers are arranged zigzag along the first direction, and coupling portions of the upper contact and the lower contact are displaced from the center of the upper contact in a second direction perpendicular to the first direction.

Abstract: Disclosed herein is a multichip package comprising an optoelectronics assembly; a socket that houses the optoelectronics assembly; the socket being in electrical communication with the optoelectronics assembly; a plate having a first surface and a second surface; the first surface being opposedly disposed to the second surface; a portion of the first surface contacting a portion of the socket to provide thermal contact between the socket and the plate; a serpentine channel being disposed between the plate and the socket to provide a passage for a communication cable that is in operative communication with the optoelectronics assembly; and a heat exchanger in thermal contact with the plate; the heat exchanger being operative to cool the multichip package.

Abstract: A semiconductor package includes a leadframe. An upper lead is disposed above the leadframe. A first die is attached to a lower surface of the upper lead to provide electrical conductivity from the first die to the upper lead. A second die is attached to the first die. A method of manufacturing a semiconductor package includes providing a leadframe having an upper lead, lower lead, and an elevated die paddle. A first die, attached to a plurality of dies in a wafer form, is attached to a second die. The first die is singulated from the plurality of dies. The first and second dies are attached to the elevated die paddle structure. The first die is wire bonded to the lower lead. An encapsulant is formed over the first and second dies. The elevated die paddle is removed to expose a surface of the upper lead and second die.

Abstract: A chip module and to a chip card with a chip module which can be bent in such a way that a cross-sectional area runs along the greatest curvature of the bending line and parallel to one side of the chip module or the chip card. The module comprises contact areas within a surrounding line which are arranged in a plane perpendicular to the cross-sectional area, the surrounding line comprising a first line portion, which is adjacent the cross-sectional area, and a second line portion, which is opposite the first line portion. Furthermore, the module comprises a component, which is positioned in such a way that a first distance between the component and the first line portion is greater than a second distance between the component and the second line portion.

Abstract: Techniques for disposing an organic semiconductor film on a receiver substrate, comprising the steps of: depositing an organic semiconductor film onto a donor substrate, the semiconductor film having a first surface facing the donor substrate and having an exposed second surface; bringing the exposed second surface adjacent a receiver substrate such that the semiconductor film is in contact with both substrates; and then, moving the donor and receiver substrates apart; and wherein a surface portion of the receiver substrate is maintained above its glass transition during the moving step. Active organic semiconductor devices.

Abstract: A multi-chip package includes a package substrate. First and second semiconductor die are formed on the package substrate. The first and the second semiconductor die are configured to communicate with each other via a high-speed serial communications protocol.