Patents Examined by Sherman Ng
  • Patent number: 12046396
    Abstract: A wiring member includes: a base member; a transmission wire body; and a wire-like transmission member having a covering provided around the transmission wire body, wherein the wire-like transmission member includes a fixing region fixed to the base member and a separating region separated from the base member, and a thermal conductive layer having more favorable thermal conductivity than the covering is formed on an outer periphery of the covering in the separating region.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: July 23, 2024
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Daichi Fukushima
  • Patent number: 12041755
    Abstract: A method for producing a power semiconductor module arrangement includes: arranging at least one semiconductor substrate in a housing, each semiconductor substrate including a first metallization layer attached to a dielectric insulation layer, the housing including a through hole extending through a component of the housing; inserting a fastener into the through hole such that an upper portion of the fastener is not inserted into the through hole; arranging a printed circuit board on the housing; arranging the housing on a mounting surface, the mounting surface comprising a hole, wherein the housing is arranged on the mounting surface such that the through hole is aligned with the hole in the mounting surface; and exerting a force on the printed circuit board such that the force causes the fastener to be pressed into the hole in the mounting surface so as to secure the housing to the mounting surface.
    Type: Grant
    Filed: December 16, 2022
    Date of Patent: July 16, 2024
    Assignee: Infineon Technologies AG
    Inventors: Regina Nottelmann, Andre Arens, Michael Ebli, Alexander Herbrandt, Ulrich Michael Georg Schwarzer, Alparslan Takkac
  • Patent number: 12041727
    Abstract: Provided are a surface-treated glass cloth that enables the reliability of a printed wiring board to be improved, a prepreg, and a printed wiring board. In the surface-treated glass cloth, a surface-treated layer contains a silane coupling agent, the amount of carbon attached of an adhering component of the surface-treated layer is in the range of 0.030 to 0.060% by mass, the arithmetic average height of the surface of the adhering component of the surface-treated layer is in the range of 1.0 to 3.0 nm, and the product of the amount of carbon attached of the adhering component and the arithmetic average height of the surface of the adhering component is in the range of 0.060 to 0.100.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: July 16, 2024
    Assignee: Nitto Boseki Co., Ltd.
    Inventors: Kazutaka Adachi, Kohei Matsumoto
  • Patent number: 12035481
    Abstract: A method for manufacturing a circuit board includes: preparing a first substrate and a second substrate, wherein: the first substrate comprises a convex post member formed at a top surface of the first substrate, and the second substrate including a first surface and a second surface opposite to the first surface, and comprising: a first metal layer formed on at least the first surface, and an opening through which a top surface of the post member is uncovered in a plan view; bonding at least a portion of a top surface of the first substrate excluding the post member and the second surface of the second substrate so that the top surface of the post member is uncovered through the opening; and forming a circuit pattern by removing a first portion of the first metal layer.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: July 9, 2024
    Assignee: NICHIA CORPORATION
    Inventor: Masakazu Sakamoto
  • Patent number: 12035484
    Abstract: A wiring circuit board includes a metal support layer, a base insulating layer disposed on one side in a thickness direction of the metal support layer, and a conductive layer disposed on one side in the thickness direction of the base insulating layer, and including a first terminal and a ground lead residual portion electrically connected to the first terminal. The base insulating layer has a through hole penetrating in the thickness direction. The ground lead residual portion has an opening continuous so as to surround the through hole.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: July 9, 2024
    Assignee: NITTO DENKO CORPORATION
    Inventors: Kenya Takimoto, Naoki Shibata, Hayato Takakura
  • Patent number: 12035477
    Abstract: An electronics module (100), especially a power electronics module, comprising a metal-ceramic substrate (1) serving as a carrier and having a ceramic element (10) and a primary component metallization (21), an insulation layer (40) directly or indirectly connected to the primary component metallization (21), and a secondary component metallization (22) which is connected to the side of the insulation layer (40) facing away from the metal-ceramic substrate (1) and is especially isolated from the primary component metallization (21) using the insulation layer (40), wherein the ceramic element (10) has a first size (L1, D1) and the insulation layer (40) has a second size (L2, D2) and a ratio of the second size (L2, D2) to the first size (L1, D1) has a value smaller than 0.8, to form an island-like insulation layer (40) on the primary component metallization (21).
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: July 9, 2024
    Assignee: ROGERS GERMANY GMBH
    Inventors: Andreas Meyer, Karsten Schmidt, Tilo Welker
  • Patent number: 12033930
    Abstract: An integrated circuit (IC) package substrate, comprising a metallization level within a dielectric material. The metallization level comprises a plurality of conductive features, each having a top surface and a sidewall surface. The top surface of a first conductive feature of the plurality of conductive features has a first average surface roughness, and the sidewall surface of a second conductive feature of the plurality of conductive features has a second average surface roughness that is less than the first average surface roughness.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: July 9, 2024
    Assignee: Intel Corporation
    Inventors: Jieying Kong, Yiyang Zhou, Suddhasattwa Nad, Jeremy Ecton, Hongxia Feng, Tarek Ibrahim, Brandon Marin, Zhiguo Qian, Sarah Blythe, Bohan Shan, Jason Steill, Sri Chaitra Jyotsna Chavali, Leonel Arana, Dingying Xu, Marcel Wall
  • Patent number: 12027451
    Abstract: A wiring substrate includes an insulating layer, a conductor layer formed on the insulating layer and including a conductor pad, and a solder resist layer formed on the insulating layer such that the solder resist layer has an opening entirely exposing an upper surface and a side surface of the conductor pad. The conductor layer is formed such that the conductor pad has a pad body extending along a surface of the insulating layer, and a protective layer covering an upper surface and a side surface of the pad body and including material different from material of the pad body, and the pad body of the conductor pad has a notch part formed at a peripheral edge portion of the pad body such that the notch part separates a lower surface of the pad body and the surface of the insulating layer and is filled with the protective layer.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: July 2, 2024
    Assignee: IBIDEN CO., LTD.
    Inventors: Shuhei Goto, Satoru Kawai
  • Patent number: 12027361
    Abstract: High temperature superconductor (HTS)-based interconnect systems comprising a cable including HTS-based interconnects are described. Each of the HTS-based interconnects includes a first portion extending from a first end towards an intermediate portion and a second portion extending from the intermediate portion to a second end. Each of the HTS-based interconnects includes a substrate layer formed in the first portion, in the intermediate portion, and in the second portion, a high temperature superconductor layer formed in at least a sub-portion of the first portion, in the intermediate portion, and in the second portion, and a metallic layer formed in the first portion and in at least a sub-portion of the intermediate portion. The HTS-based interconnect system includes a thermal load management system configured to maintain the intermediate portion of each of the HTS-based interconnects at a predetermined temperature in a range between a temperature of 60 kelvin and 92 kelvin.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: July 2, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Dawson Yee, Craig S. Ranta, Cliff C. Lee, Douglas P. Kelley, Matthew David Turner, David B. Tuckerman
  • Patent number: 12022621
    Abstract: A method of manufacturing a printed circuit board includes: forming first and second resist films, respectively having first and second openings exposing a first metal layer disposed on one surface of an insulating layer; forming a second metal layer on the first metal layer, exposed through the first and second openings, to fill at least a portion of each of the first and second openings; and removing the first and second resist films. The first and second openings have different widths in a cross-section.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: June 25, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Mi Jeong Jeon, Tae Hee Yoo, Hyun Seok Yang, In Jae Chung
  • Patent number: 12013732
    Abstract: An information handling system includes a first set of components, a second set of components, and a hybrid cooling system. The hybrid cooling system includes a fan structure, a liquid cooling system, and a fan insert. The fan structure includes multiple cooling fans to provide air cooling to the first components of the information handling system. The liquid cooling system provides liquid cooling to one or more of the second components. The liquid cooling system includes a first liquid line routed through an empty fan cavity of the fan structure. The fan insert is located within the empty fan cavity and provides a seal against air-bypass and recirculation within the information handling system.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: June 18, 2024
    Assignee: Dell Products L.P.
    Inventors: Walter R. Carver, Douglas S. Haunsperger
  • Patent number: 12014846
    Abstract: A wiring member includes: a wire-like transmission member including a transmission wire body and a covering for covering the transmission wire body; a sheet material to which the wire-like transmission member is fixed; and a cover formed of a material different from a material of the covering, covering the wire-like transmission member from a side opposite to the sheet material, and fixed to the sheet material, wherein the sheet material includes a first fixing part to which the covering is directly fixed and a second fixing part which is directly fixed to the cover more easily than the first fixing part and to which the cover is directly fixed.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: June 18, 2024
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Haruka Nakano, Motohiro Yokoi, Kenta Ito, Takuya Kaba, Suguru Yasuda, Makoto Higashikozono, Yoshitaka Kami, Yasushi Nomura, Sofia Barillaro
  • Patent number: 12015336
    Abstract: A power semiconductor package comprises a lead frame, a semiconductor chip, and a molding encapsulation. The lead frame comprises an elevated section comprising a source section; a drain section; and a plurality of leads. The semiconductor chip includes a metal-oxide-semiconductor field-effect transistor (MOSFET) disposed over the lead frame. The semiconductor chip comprises a source electrode, a drain electrode, and a gate electrode. The source electrode of the semiconductor chip is electrically and mechanically connected to the source section of the elevated section of the lead frame. The semiconductor chip is served as a low side field-effect transistor as a flipped-chip connected to a heat sink by a first thermal interface material. A high side field-effect transistor is connected to the heat sink by a second thermal interface material. The low side field-effect transistor and the high side field-effect transistor are mounted on a printed circuit board.
    Type: Grant
    Filed: September 1, 2023
    Date of Patent: June 18, 2024
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Ziwei Yu, Lin Chen, Zhiqiang Niu
  • Patent number: 12016118
    Abstract: Printed circuit boards may be formed using ceramic substrates with high thermal conductivity to facilitate heat dissipation. Metal nanoparticles, such as copper nanoparticles, may be used to form conductive traces and fill through-plane vias upon the ceramic substrates. Multi-layer printed circuit boards may comprise two or more ceramic substrates adhered together, wherein each ceramic substrate has one or more conductive traces defined thereon and the one or more conductive traces are formed through consolidation of metal nanoparticles. The one or more conductive traces in a first ceramic substrate layer are in electrical communication with at least one second ceramic substrate layer adjacent thereto.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: June 18, 2024
    Assignee: Kuprion Inc.
    Inventors: Alfred A. Zinn, Khanh Nguyen
  • Patent number: 12016125
    Abstract: An electric component includes a printed circuit board with each of a pair of surfaces serving as a component mounting surface. The component mounting surface has a predetermined region on which electronic components are coated with a resin. A predetermined one of the electronic components in the region is not covered with the resin at a portion above a predetermined height from the component mounting surface.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: June 18, 2024
    Assignee: Daikin Industries, Ltd.
    Inventor: Mitsuhiro Tanaka
  • Patent number: 12009138
    Abstract: A magnetic device includes a magnetic core assembly, a first secondary winding, a second secondary winding and a primary winding. The magnetic core assembly includes a first magnetic leg, a second magnetic leg and a third magnetic leg. The first to third magnetic legs are arranged in sequence. The second magnetic leg is disposed between the first magnetic leg and the third magnetic leg. The first secondary winding is disposed between the first magnetic leg and the second magnetic leg, and the second secondary winding is disposed between the second magnetic leg and the third magnetic leg. A first terminal of the primary winding is disposed between the first magnetic leg and the second magnetic leg, and a second terminal of the primary winding is disposed between the second magnetic leg and the third magnetic leg.
    Type: Grant
    Filed: November 15, 2022
    Date of Patent: June 11, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Da Jin, Yang Leng, Zhongwang Yang, Yahong Xiong
  • Patent number: 12003185
    Abstract: A modular switching cell of a high voltage direct current power converter has a modular switching cell that includes a base module, which has: a first switching unit; a second switching unit; a first capacitor; and a second capacitor. The first switching unit, the second switching unit, the first capacitor, and the second capacitor are mounted on a chassis. The base module is configured to receive at least three different busbar sets, each of the busbar sets having a plurality of busbars for interconnecting the first switching unit, the second switching unit, the first capacitor, and the second capacitor to form one of: two parallel half bridge circuits between a first cell terminal and a second cell terminal; two serial half bridge circuits between the first cell terminal and the second cell terminal; or a full bridge circuit between the first cell terminal and the second cell terminal.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: June 4, 2024
    Assignee: MASCHINENFABRIK REINHAUSEN GMBH
    Inventor: Angus Bryant
  • Patent number: 11994723
    Abstract: An apparatus includes a body with an opening through the body, the opening corresponding to dimensions of a cable to be connected to a circuit board and a flat surface to abut the circuit board. The apparatus further includes one or more attachment mechanisms to attach the body to the circuit board.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: May 28, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: Eric Lotter, Aditya Prabhakar, Paula Zubiri Rivero
  • Patent number: 11991838
    Abstract: An embedded circuit board made without gas bubbles or significant internal gaps according to a manufacturing method which is here disclosed comprises an inner layer assembly, an embedded element, and first and second insulating elements. The inner layer assembly comprises a first main portion with opposing first and second surfaces, a first groove not extending to the second surface is positioned at the first surface. A first opening penetrates the second surface, and the first opening and the first groove are connected. The first groove carries electronic elements for embedment. The first insulating element covers the first surface and a surface of the embedded element away from the second surface. The second insulating element covers the second surface and extends into the first opening to be in contact with the embedded element.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: May 21, 2024
    Assignees: QING DING PRECISION ELECTRONICS (HUAIAN) CO., LTD, Avary Holding (Shenzhen) Co., Limited.
    Inventors: Cheng-Yi Yang, Hao-Wen Zhong, Biao Li, Ming-Jaan Ho, Ning Hou
  • Patent number: 11985766
    Abstract: A board shield (52) covers a region in which an electronic part is mounted on a lower surface of a circuit board (50). A memory housing chamber (R1) capable of housing a semiconductor memory is secured on the lower side of the circuit board. The board shield (52) includes a shield wall (52e) along the memory housing chamber (R1). With this, it is possible to protect the semiconductor memory while suppressing an increase in the number of parts.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: May 14, 2024
    Assignee: Sony Interactive Entertainment Inc.
    Inventors: Katsushi Ito, Yasuhiro Ootori, Nobuyuki Sugawara