Patents Examined by Sherman Ng
  • Patent number: 11562835
    Abstract: A method of extending the usable length of a power-over-ethernet cable includes the steps of providing twisted pairs of wires with the conductor of each wire being a 20 AWG or 22 AWG conductor and terminating the cable at an RJ-45 style connector. The connector for the 20 AWG conductors has an insert therein with holes that can accommodate 20 AWG conductors. FEP, PVC or PP insulation may surround each conductor.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: January 24, 2023
    Assignee: Paige Electric Company, LP
    Inventor: Francis X. Conaty
  • Patent number: 11558956
    Abstract: A generator control unit (GCU) having thermal control includes a GCU housing having a first side and a second side. A printed wiring board (PWB) is within the GCU housing between the first side and the second side. The PWB includes a component side that faces a first side of the GCU housing. At least one through via is positioned through a thickness of the PWB. At least one boss is positioned on the component side of the PWB. The at least one boss extends from a component of the PWB to the first side of the GCU housing.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: January 17, 2023
    Assignee: Hamilton Sundstrand Corporation
    Inventors: Steven E. Larson, Eric A. Carter, Ethan Johnson
  • Patent number: 11558955
    Abstract: A quantum mechanical circuit includes a substrate; a first electrical conductor and a second electrical conductor provided on the substrate and spaced apart to provide a gap therebetween; and a third electrical conductor to electrically connect the first electrical conductor and the second electrical conductor. The third electrical conductor is a poor thermal conductor.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: January 17, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Trevor Timpane, Layne A. Berge, Patryk Gumann, Sean Hart, Curtis Eugene Larsen, Michael Good
  • Patent number: 11553595
    Abstract: A printed circuit board comprises N power switching cells operating in parallel and respectively comprising a transistor leg, at least one decoupling capacitor and a gate driver circuit. Each transistor leg comprises respective first and second transistors in series, a drain of the first transistor being connected to a positive DC line, a source of the second transistor being connected to a negative DC line, a source of the first transistor being connected to a drain of the second through a connection middle-point connected to an output terminal. Each gate driver circuit controls respective switching ON and OFF of the corresponding first and second transistors. The N transistor legs of the corresponding N power switching cells are positioned to substantially form a convex polygon having N edges of substantially the same length, each one of the N transistor legs being positioned along one of the edges of the convex polygon.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: January 10, 2023
    Assignee: IDÉNERGIE INC.
    Inventors: Handy Fortin-Blanchette, Pierre Blanchet
  • Patent number: 11552020
    Abstract: A semiconductor composite device is provided that includes a voltage regulator, a package board, and a load, and converts an input DC voltage into a different DC voltage to supply the converted DC voltage to the load. The VR includes a semiconductor active element. The package board includes a C layer in which a capacitor is formed, and an L layer in which an inductor is formed. A plurality of through holes penetrate the C layer and the L layer in a direction perpendicular to the mounting face in the package board. The capacitor is connected to the load through the through hole. The inductor is connected to the load through the through hole and to the VR through the through hole.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: January 10, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Koshi Himeda, Tatsuya Kitamura, Chiharu Sakaki, Shinya Kiyono, Sho Fujita, Atsushi Yamamoto, Takeshi Furukawa, Kenji Nishiyama, Tatsuya Funaki, Kinya Aoki
  • Patent number: 11545297
    Abstract: Embodiments of the disclosure relate to apparatuses for enhanced thermal management of an inductor assembly using functionally-graded thermal vias for heat flow control in the windings of the inductor. In one embodiment, a PCB for an inductor assembly includes a top surface and a bottom surface. Two or more electrically-conductive layers are embedded within the PCB and stacked vertically between the top surface and the bottom surface. The two or more electrically-conductive layers are electrically connected to form an inductor winding. A plurality of thermal vias thermally connects each of the two or more electrically-conductive layers to a cold plate thermally connected to the bottom surface. A number of thermal vias thermally connecting each electrically-conductive layer to the cold plate is directly proportional to a predetermined rate of heat dissipation from the electrically-conductive layer.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: January 3, 2023
    Assignees: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC., UNIVERSITY OF COLORADO BOULDER
    Inventors: Ercan Dede, Yucheng Gao, Vivek Sankaranarayanan, Aritra Ghosh, Robert Erickson, Dragan Maksimovic
  • Patent number: 11533824
    Abstract: A method for producing a power semiconductor module arrangement includes: arranging a semiconductor substrate in a housing, the housing including a through hole extending through a component of the housing; inserting a pin or bolt into the through hole such that an upper end of the pin/bolt is not inserted into the through hole; arranging a printed circuit board on the housing; arranging the housing on a heat sink having a hole, the housing being arranged on the heat sink such that the through hole is aligned with the hole in the heat sink; and by way of a first pressing tool, exerting a force on a defined contact area of the printed circuit board and pressing the pin/bolt into the hole in the heat sink, wherein the defined contact area is arranged directly above the pin/bolt.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: December 20, 2022
    Assignee: Infineon Technologies AG
    Inventors: Regina Nottelmann, Andre Arens, Michael Ebli, Alexander Herbrandt, Ulrich Michael Georg Schwarzer, Alparslan Takkac
  • Patent number: 11533811
    Abstract: An electronic device includes a substrate, multiple side wires, and a protection structure. The substrate has a first main surface, a side surface, and a first multi-turning surface connected between the first main surface and the side surface. The first multi-turning surface includes multiple first turning surfaces with differing normal directions. The side wires are disposed on the substrate. Each of the side wires extends from the first main surface over the first multi-turning surface to the side surface. The protection structure is disposed on the substrate and includes a wire protection part covering the side wires. The wire protection part has a first thickness at the side surface, a second thickness at the first main surface, and a third thickness at at least one of the first turning surfaces. The first thickness is greater than the second thickness, and the second thickness is greater than the third thickness.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: December 20, 2022
    Assignee: Au Optronics Corporation
    Inventors: Yun Cheng, Hao-An Chuang, Hsi-Hung Chen, Chun-Yueh Hou, Fan-Yu Chen
  • Patent number: 11533806
    Abstract: A filter includes a first input/output electrode and the second input/output electrode, and is arranged on a first main surface of a mounting substrate. The mounting substrate includes a first land electrode, a second land electrode, a ground terminal, and a plurality of via conductors. The first land electrode is connected to the first input/output electrode. The second land electrode is connected to the second input/output electrode. The ground terminal is located closer to a second main surface side than the first main surface in a thickness direction of the mounting substrate. The plurality of via conductors is arranged between the first main surface and the second main surface, and is connected to the ground terminal. The plurality of via conductors is located between the first land electrode and the second land electrode in a plan view from the thickness direction of the mounting substrate.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: December 20, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hiroshi Matsubara, Masanori Kato, Yukiteru Sugaya, Syunsuke Kido
  • Patent number: 11532543
    Abstract: A package carrier includes a substrate, at least one interposer disposed in at least one opening of the substrate, a conductive structure layer, a first build-up structure, and a second build-up structure. The interposer includes a glass substrate, at least one conductive via, at least one first pad, and at least one second pad. The conductive via passes through the glass substrate, and the first and the second pads are disposed respectively on an upper surface and a lower surface of the glass substrate opposite to each other and are connected to opposite ends of the conductive via. The conductive structure layer is disposed on the substrate and is structurally and electrically connected to the first and the second pads. The first and the second build-up structures are disposed respectively on the first and the second surfaces of the substrate and are electrically connected to the conductive structure layer.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: December 20, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Wei-Ti Lin, Chun-Hsien Chien, Yu-Hua Chen
  • Patent number: 11528811
    Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: December 13, 2022
    Assignee: Intel Corporation
    Inventors: Jeremy Ecton, Nicholas Haehn, Oscar Ojeda, Arnab Roy, Timothy White, Suddhasattwa Nad, Hsin-Wei Wang
  • Patent number: 11519858
    Abstract: An optical sensor includes a detector having a printed circuit board (PCB) and an inductive loop. The printed circuit board (PCB) has a photodiode cathode pad with a photodiode. The inductive loop is arranged around at least part of the photodiode cathode pad, and configured to receive inductive loop inducing signaling, and provide inductive loop signaling around the at least part of the photodiode cathode pad to provide inductive on the PCB to reduce or substantially eliminate unwanted electrical interference in electrical photodiode signaling provided from the photodiode. The inductive loop includes a trace and at least one via. The trace has a route along a signal path from a transistor collector pin around an LED anode pad. The at least one via is placed between LED anode pads to route the trace on a top side of the PCB, and the trace is routed alongside, near and around the photodiode cathode pad back to the LED anode of the LED anode pad.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: December 6, 2022
    Assignee: YSI, INC.
    Inventors: Kevin R. Flanagan, Steven M. Parmley, Douglas J. Posey, Michael Leiss
  • Patent number: 11521912
    Abstract: An electronic element mounting substrate includes: a first substrate including a first principal face; a second substrate located inside the first substrate in a plan view of the electronic element mounting substrate, the second substrate being made of a carbon material; a third substrate located between the first substrate and the second substrate in the plan view, the third substrate being made of a carbon material; and a first mounting portion for mounting a first electronic element, the first mounting portion being located on the first principal face side in a thickness direction of the substrate. The second substrate and the third substrate each have a low heat conduction direction and a high heat conduction direction. The second substrate and the third substrate is arranged so that the low heat conduction directions thereof are perpendicular to each other, and the high heat conduction directions thereof are perpendicular to each other.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: December 6, 2022
    Assignee: KYOCERA CORPORATION
    Inventors: Noboru Kitazumi, Yousuke Moriyama
  • Patent number: 11523505
    Abstract: An embedded component structure includes a circuit board, an electronic component, a first conductive terminal, and a second conductive terminal. The circuit board includes a first electrical connection layer and a second electrical connection layer. The electronic component is embedded in the circuit board and includes a first contact and a second contact. The first conductive terminal and the second conductive terminal respectively at least cover a part of top surfaces and side walls of the first contact and the second contact, and the first electrical connection layer and the second electrical connection layer are respectively electrically connected to the first contact and the second contact through the first conductive terminal and the second conductive terminal. A method for manufacturing an embedded component structure is also provided.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: December 6, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Yu-Shen Chen, I-Ta Tsai, Chien-Chih Chen
  • Patent number: 11523495
    Abstract: A multilayer PCB structure includes a core layer, a first layer on a first surface of the core layer, a second layer on a second surface of the core layer, and a thermally conductive material in the core layer. The first surface and the second surface of the core layer are opposite to each other, and a window is formed on the second layer by removing part of the second layer. The window of the second layer exposes part of the core layer below the thermally conductive material.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: December 6, 2022
    Assignee: Prime World International Holdings Ltd.
    Inventors: Che-Shou Yeh, Ling-An Kung, Cheng-Ta Tsai, Shih-Cheng Lin
  • Patent number: 11515060
    Abstract: A communications cable is provided that includes a pair of twisted pair of wires, each coated with a fluoropolymer insulator. The twisted pair of wires is configured to carry a differential signal, such as a differential data signal and/or a differential power signal. The fluoropolymers are highly effective insulators and significantly reduce both the effects of internal and external electromagnetic interference while maintaining low cable attenuation, even when operating within a temperature range of ?40° C. to 150° C.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: November 29, 2022
    Assignees: DAIKIN AMERICA, INC., DAIKIN INDUSTRIES, LTD.
    Inventor: Daniel J. Kennefick
  • Patent number: 11516904
    Abstract: Provided are flexible hybrid interconnect circuits and methods of forming thereof. A flexible hybrid interconnect circuit comprises multiple conductive layers, stacked and spaced apart along the thickness of the circuit. Each conductive layer comprises one or more conductive elements, one of which is operable as a high frequency (HF) signal line. Other conductive elements, in the same and other conductive layers, form an electromagnetic shield around the HF signal line. Some conductive elements in the same circuit are used for electrical power transmission. All conductive elements are supported by one or more inner dielectric layers and enclosed by outer dielectric layers. The overall stack is thin and flexible and may be conformally attached to a non-planar surface. Each conductive layer may be formed by patterning the same metallic sheet. Multiple pattern sheets are laminated together with inner and outer dielectric layers to form a flexible hybrid interconnect circuit.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: November 29, 2022
    Assignee: CelLink Corporation
    Inventors: Kevin Michael Coakley, Malcolm Parker Brown, Jose Juarez, Emily Hernandez, Joseph Pratt, Peter Stone, Vidya Viswanath, Will Findlay
  • Patent number: 11516558
    Abstract: A module for a networking node is disclosed. The module includes a Printed Circuit Board (“PCB”), one or more circuits mounted to the PCB and a faceplate. The faceplate includes a middle plate, a first side plate, and a second side plate. The first side plate extends from the middle plate at an obtuse angle relative to the middle plate towards a first side and back of the module. The second side plate extends from the middle plate, opposite to the first side plate, at an obtuse angle relative to the middle plate towards a second side and the back of the module.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: November 29, 2022
    Assignee: Ciena Corporation
    Inventors: Simon J. E. Shearman, Fabien Colton, Daniel Rivaud, Michael R. Bishop
  • Patent number: 11515804
    Abstract: An electric circuit for a power converter having a substrate having a first face on which electronic components are mounted and a second face intended to cooperate with a cooling system, the substrate having a stack of conductive layers made of electrically and thermally conductive material and at least one insulating layer made of electrically insulating material, two successive conductive layers being separated by an insulating layer, and the conductive and insulating layers extending in parallel planes and being mechanically associated together. Each conductive layer has two opposite faces parallel to the plane in which the first face of the substrate extends and includes, on at least one of its two faces, at least one boss extending in a direction perpendicular to the plane, the at least one boss passing through at least one other conductive layer and opening out onto the first or the second face of the substrate.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: November 29, 2022
    Assignees: SAFRAN ELECTRICAL & POWER, ELVIA PRINTED CIRCUIT BOARDS
    Inventors: Philippe Poret, Olivier Belnoue
  • Patent number: 11510317
    Abstract: A circuit board may include a plurality of electrically-conductive layers separated and supported by layers of insulating material laminated together and a via electrically coupled to a first layer of the circuit board and coupled to a second layer of the circuit board, the via comprising a first via portion comprising electrically-conductive material and having a first diameter and a first depth from a surface of the circuit board and a second via portion comprising electrically-conductive material and having a second diameter smaller than the first diameter and a second depth from the first depth.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: November 22, 2022
    Assignee: Dell Products L.P.
    Inventors: Sandor Farkas, Bhyrav Mutnury, Steven Ethridge