Patents Examined by Sherman Ng
  • Patent number: 12144109
    Abstract: A printed circuit board is provided. The printed circuit board includes: an extending region extending along one direction, and a bending region configured to bend with respect to the extending region. The extending region and the bending region includes a non-conductive layer, a first conductive layer disposed on one surface of the non-conductive layer, a second conductive layer disposed on the other surface of the non-conductive layer, and at least one via hole penetrating the non-conductive layer, the first conductive layer, and the second conductive layer. In the bending region, a cross-sectional area of the via hole in contact with the first conductive layer is less than a cross-sectional area of the via hole in contact with the second conductive layer.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: November 12, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngsun Lee, Sungwon Park, Eunseok Hong
  • Patent number: 12144105
    Abstract: A wiring board according to the present disclosure includes a core layer including core electrical conductor layers on upper and lower surfaces of a core insulating layer, a first build-up portion, a second build-up portion, a first mounting region, and a second mounting region. The first build-up portion includes a first build-up insulating layer and a first build-up electrical conductor layer connected to the first mounting region. The second build-up portion includes a second build-up insulating layer and a second build-up electrical conductor layer connected to the second mounting region. The second build-up insulating layer includes a margin for adhesion between the second build-up insulating layers or between the second build-up insulating layer and the core insulating layer. The second build-up electrical conductor layer includes an electrical conductor layer for grounding, a first opening, and a signal pad located inside the first opening.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: November 12, 2024
    Assignee: KYOCERA CORPORATION
    Inventor: Toshihiro Hiwatashi
  • Patent number: 12144114
    Abstract: An electronic element mounting substrate includes a substrate including a first layer, a second layer located on a lower surface of the first layer, and a third layer located on a lower surface of the second layer, and on which an electronic element is to be mounted. The substrate has a via conductor that passes through the first layer to the third layer in a vertical direction. The substrate includes respective electrical conductor layers located between the respective layers and connected to the via conductor in a plan perspective. Each electrical conductor layer includes a land portion surrounding the via conductor, a clearance portion surrounding the land portion, and a peripheral portion surrounding the clearance portion and electrically insulated from the land portion with the clearance portion interposed between the land portion and the peripheral portion.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: November 12, 2024
    Assignee: KYOCERA CORPORATION
    Inventor: Kanae Horiuchi
  • Patent number: 12144162
    Abstract: An object is to provide an electromagnetic wave absorber that has excellent performance in absorbing high-frequency electromagnetic waves of 60 GHz to 120 GHz incident thereon, and further has flexibility and can be installed on various curved surfaces. Conventional problems have been made solvable by an electromagnetic wave absorber that is a structure formed by folding a sheet 1 into the form of pleats, the sheet containing a conductive material and having a surface resistance of 10?/? to 104?/?, in which slits 2 are perforated non-parallel to a folded ridgeline R.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: November 12, 2024
    Assignee: HIROSE PAPER MFG CO., LTD.
    Inventors: Tomoya Nishiuchi, Yoshiki Mizuno
  • Patent number: 12142389
    Abstract: A method of extending the usable length of a power-over-ethernet cable includes the steps of providing twisted pairs of wires with the conductor of each wire being a 20 AWG or 22 AWG conductor and terminating the cable at an RJ-45 style connector. The connector for the 20 AWG conductors has an insert therein with holes that can accommodate 20 AWG conductors. FEP, PVC or PP insulation may surround each conductor.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: November 12, 2024
    Assignee: Paige Electric Company, LP
    Inventor: Francis X. Conaty
  • Patent number: 12137522
    Abstract: A wiring circuit board includes a mounting region for mounting an electronic element and a circuit region surrounding the mounting region. The mounting region includes a terminal. The circuit region includes a circuit to be electrically connected to the terminal. The circuit region includes a metal support layer, a base insulating layer, and a conductive layer including the circuit. The mounting region does not include the metal support layer and includes a base insulating layer having an opening portion, and the conductive layer including the terminal. The terminal is disposed in the opening portion of the base insulating layer.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: November 5, 2024
    Assignee: NITTO DENKO CORPORATION
    Inventors: Rihito Fukushima, Shusaku Shibata, Teppei Niino
  • Patent number: 12137516
    Abstract: One way to stop electromagnetic fields from leaking outside of a module is an electric wall. Embodiments of the present disclosure are directed to emulating an electric wall with through vias. The through vias may be arranged around cavities in the printed circuit board. The density of the through vias may be selected based on an expected wavelength of the electromagnetic fields. The printed circuit board may then self-isolate components within the cavities from the electromagnetic fields.
    Type: Grant
    Filed: October 6, 2022
    Date of Patent: November 5, 2024
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Hongya Xu, Valter Pasku, Martin Handtmann, Lueder Elbrecht, Li Sun
  • Patent number: 12133330
    Abstract: A wiring substrate includes an insulating layer, a pad in a via hole piercing through the insulating layer and exposed at a first surface of the insulating layer, a via conductor on the pad in the via hole, and a wiring part on a second surface of the insulating layer facing away from the first surface. The wiring part is connected to the pad through the via conductor in the via hole.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: October 29, 2024
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Akihiro Takeuchi
  • Patent number: 12127346
    Abstract: A substrate includes a first connector fittable to a connector of a host device. The first connector includes a plurality of connector terminals arranged in a first direction and a substrate portion including a surface S1 provided with the plurality of connector terminals and extending in the first direction. The substrate portion includes a surface S3 perpendicular to the surface S1, a first protrusion provided on the surface S3 and protruding in the first direction, a surface S4 located on an opposite side of the surface S3, and a second protrusion provided on the surface S4 and protruding in a direction opposite to the first direction.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: October 22, 2024
    Assignee: KIOXIA CORPORATION
    Inventor: Kazuyuki Niitsuma
  • Patent number: 12120829
    Abstract: An assembly sheet as a wiring circuit board assembly sheet includes a metal substrate, a wiring circuit structure portion, and a dummy structure portion. The metal substrate includes a product region and a frame region adjacent thereto. The wiring circuit structure portion is disposed on one surface in a thickness direction of the metal substrate in the product region, and includes a terminal portion. The dummy structure portion is disposed on one surface in the thickness direction of the metal substrate in the frame region, includes a plurality of conductive layers aligned in the thickness direction, and has a greater height above the metal substrate than the terminal portion.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: October 15, 2024
    Assignee: NITTO DENKO CORPORATION
    Inventors: Shusaku Shibata, Shun Shiga, Teppei Niino
  • Patent number: 12116027
    Abstract: A railway termination shunt enclosure including one or more receptacles, each of the one or more receptacles being configured to receive a termination shunt. The enclosure also includes at least one mounting surface and a connector assembly rotatably attaching the one or more receptacles to one or more of the at least one mounting surface.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: October 15, 2024
    Assignee: C.D.L. Electric Company, Inc.
    Inventors: Devin Steven Sage, Marco Antonio Ibarra, Angel Gustavo Cereceres Pena
  • Patent number: 12120818
    Abstract: Disclosed is a printed circuit board according to an embodiment. The printed circuit board comprises: a base board; a metal layer, including a pad and a metal line formed in the base board; a solder resist layer that is formed on the base board on which the metal layer is formed and has an opening through which the surface of the metal line is exposed; and an underfill that is formed between the solder resist layer and a semiconductor chip electrically connected to the pad and includes a blocking area formed in the opening.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: October 15, 2024
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Myung Gu Kang
  • Patent number: 12112668
    Abstract: According to one embodiment, a flexible substrate includes a first protective member including a first surface, a line portion including a flexible insulating base located on the first surface and a wiring layer disposed on the insulating base and a second protective member covering the line portion, and the first protective member includes a valley portion and a peak portion in the first surface, and the line portion is formed in a wavy shape and located on the valley portion and the peak portion.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: October 8, 2024
    Assignee: JAPAN DISPLAY INC.
    Inventors: Youhei Iwai, Takumi Sano
  • Patent number: 12114417
    Abstract: A heat radiating substrate (10) includes an insulating layer (11) and a circuit pattern (20) of a metal formed on the insulating layer (11) in direct contact with the insulating layer (11), in which a side surface (that is, metal layer side surface (23)) of the circuit pattern (20) has a region in which an angle ? formed by a surface (insulating layer upper surface (11a)) of the insulating layer (11) (insulating substrate) and a tangential line L at a middle portion (X1) in a height direction in a cross-sectional view perpendicular to an extending direction of the metal is 80 degrees or more and 100 degrees or less.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: October 8, 2024
    Assignee: SUMITOMO BAKELITE CO., LTD.
    Inventor: Nobuo Tagashira
  • Patent number: 12114455
    Abstract: Disclosed is a circuit unit with a novel structure that can counter the heat generation by resistors while suppressing an increase in size and cost of the circuit unit. A circuit unit includes a wiring member, a lower case that holds the wiring member, an upper case that covers the lower case, and resistors connected to the wiring member, wherein the upper case include wall portions that surround peripheries of the resistors, and wherein, in a first orthogonal direction orthogonal to the longitudinal direction of the resistors, the separation distance between intermediate portions in the longitudinal direction of the resistors and the wall portions of the upper case is greater than the separation distance between end portions in the longitudinal direction of the resistors and the wall portions of the upper case.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: October 8, 2024
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yusuke Isaji, Hitoshi Takeda
  • Patent number: 12114437
    Abstract: Disclosed is a method for manufacturing a wiring structure including a step of forming a wiring on an insulating resin layer. The step of forming the wiring includes: forming a modified region including pores in a surface layer of the insulating resin layer by treating a surface of the insulating resin layer with a treatment method including surface modification; forming a seed layer on the surface of the insulating resin layer by sputtering; and forming the wiring on the seed layer by electrolytic copper plating.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: October 8, 2024
    Assignee: RESONAC CORPORATION
    Inventors: Masaya Toba, Kazuyuki Mitsukura
  • Patent number: 12114436
    Abstract: A composite circuit board includes a flexible board, rigid boards, adhesive layers, and protection glue; the adhesive layers are sandwiched between the rigid boards and the flexible board and used for bonding the rigid boards and the flexible board; the rigid boards are provided with step slots passing through the rigid boards; the adhesive layers are provided with through slots passing through the adhesive layers; the step slots and the through slots are communicated with each other to form a thinning recess; the thinning recess exposes the flexible board; and the protection glue covers steps of the thinning recess and at least a portion of the exposed area of the flexible board.
    Type: Grant
    Filed: November 10, 2022
    Date of Patent: October 8, 2024
    Assignee: SHENNAN CIRCUITS CO., LTD.
    Inventors: Zhicheng Yang, Xianyou Deng, Jinfeng Liu, Hegen Zhang, Tao Luo, Zhishen Wang
  • Patent number: 12112894
    Abstract: A multilayer capacitor includes a body including a capacitance formation region in which at least one first internal electrode and at least one second internal electrode are alternately stacked in a first direction with at least one dielectric layer interposed therebetween, and first and second external electrodes disposed on the body and spaced apart from each other to be connected to the at least one first internal electrode and the at least one second internal electrode, wherein a portion of the at least one first internal electrode and a portion of the at least one second internal electrode overlap each other in the first direction, the capacitance formation region further includes a third internal electrode connected to the first external electrode, a fourth internal electrode connected to the second external electrode, and a fifth internal electrode not connected to the first and second external electrodes and overlapping each of the third and fourth internal electrodes in the first direction, an intern
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: October 8, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Min Jun Kim
  • Patent number: 12108541
    Abstract: A welding structure and a display module. The welding structure includes: an output carrier, arranged with a first welding area on a side edge of the output carrier; an input carrier. A first end of the input carrier is arranged with a second welding area, the second welding area being electrically connected to the first welding area; an orthographic projection of the first end of the input carrier on the output carrier is disposed beyond the first welding area; and at least one set of a first support member and a second support member. The first support member is disposed on the input carrier and at a position of the first end beyond the first welding area; the second support member is disposed on the output carrier and opposite to the first support member.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: October 1, 2024
    Assignee: GUANGZHOU GOVISIONOX TECHNOLOGY CO., LTD.
    Inventor: Yangchun Lin
  • Patent number: 12101878
    Abstract: A circuit board according to an embodiments includes an insulating portion comprising a plurality of insulating layers, wherein the insulating portion includes: a first insulating portion; a second insulating portion disposed on the first insulating portion and having a coefficient of thermal expansion corresponding to the first insulating portion; and a third insulating portion disposed under the first insulating portion and having a coefficient of thermal expansion corresponding to the first insulating portion; wherein the first insulating portion includes a prepreg including glass fibers, and wherein the second and third insulating portions include a resin coated copper (RCC) with a coefficient of thermal expansion in the range of 10 to 65 (10?6 m/m·k).
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: September 24, 2024
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Dong Hwa Lee, Yong Suk Kim