Patents Examined by Sherman Ng
  • Patent number: 11191179
    Abstract: The ground connection between the circuit card and the housing and the housing connection side is implemented by at least one plug-in connection of variable insertion depth. This design is particularly advantageous for producing corresponding devices in an automated manner because, owing to the assembly of the devices, the contact-connection of the circuit card to ground also takes place automatically, specifically as desired in the advantageous form of meshed grounding with simultaneous compensation of the housing tolerances which is made possible by the plug-in connection of variable insertion depth.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: November 30, 2021
    Inventors: Volker Klanke, Christine Wulf, Peter Doeding, Andreas Loesch
  • Patent number: 11191151
    Abstract: A device may include a substrate having a first surface and a second surface, a first conductive terminal disposed over the first surface, a second conductive terminal spaced apart from the first conductive terminal in a first direction and disposed over the first surface, a first conductive auxiliary pattern disposed below the first conductive terminal and overlapping with the first conductive terminal, the first conductive auxiliary pattern being coupled to the second conductive terminal, and a second conductive auxiliary pattern disposed below the second conductive terminal and overlapping with the second conducive terminal, the second conductive auxiliary pattern being coupled to the first conductive terminal.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: November 30, 2021
    Assignee: SK hynix Inc.
    Inventors: Kyu Yong Choi, Jin Ho Bae, Yu Jeong Choe
  • Patent number: 11191177
    Abstract: An electronic device including a waterproof structure is provided. The electronic device includes a housing that includes a first face, a second face that faces in a direction substantially opposite to the first face, and a side surface that at least partially encloses a space between the first face and the second face, a middle plate arranged between the first face and the second face inside the housing to be substantially parallel to the first face, extending from the side surface, and including at least one opening, a printed circuit board arranged between the middle plate and the second face, a display arranged between the middle plate and the first face, and including a face directed toward the second face, and a seal member configured to hermetically seal the at least one opening of the middle plate, and arranged between the face of the display and the middle plate.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: November 30, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Min Choi, Woong-Chan Kim, Daehyeong Park, Sung-Gun Cho, Sung-Joo Cho, Young-Sik Choi, Kwang-Hwan Kim, Soonwoong Yang, Min-Sung Lee, Seungjoon Lee, Yuchul Chang
  • Patent number: 11191194
    Abstract: The disclosure provides a display device, including a display panel, a flexible circuit board (FCB), a printed circuit board (PCB), and a source driver chip. The PCB is connected to the display panel by the FCB, the source driver chip is bonded to a front side of the PCB, and an exposed copper area is disposed on a backside of the PCB corresponding to the source driver chip. Therefore, heat dissipation effect of a chip is improved, production costs are reduced, and working stability of products is ensured.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: November 30, 2021
    Assignee: TCL China Star Optoelectronics Technology Co., Ltd.
    Inventor: Xiaoli Fu
  • Patent number: 11189580
    Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). For example, in some embodiments, an IC package support may include: a first conductive structure in a dielectric material; a second conductive structure in the dielectric material; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a polymer, and the material is different from the dielectric material. The material may act as a dielectric material below a trigger voltage, and as a conductive material above the trigger voltage.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: November 30, 2021
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Krishna Bharath, Feras Eid, Johanna M. Swan, Aleksandar Aleksov, Veronica Aleman Strong
  • Patent number: 11183447
    Abstract: A flip-chip package substrate and a method for fabricating the same are provided. An insulation layer is formed on two opposing sides of a middle layer to form a composite core structure and increase the rigidity of the flip-chip package substrate. Therefore, the core structure can be made thinner. The conductive structures can also have a smaller end size, and more conductive points can be disposed within a unit area. Therefore, a circuit structure can be produced that have a fine line pitch and a high wiring density, satisfy the packaging demands of highly integrated circuit/large size substrate, and avoid an electronic package from being warpage.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: November 23, 2021
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu
  • Patent number: 11183446
    Abstract: X.5 layer substrates that do not use an embedded traces substrate process during formation may produce a high yield with relaxed L/S in a short manufacturing time (only 4× lamination process without a detach process) at a low cost. For example, a substrate may include an mSAP, two landing pads, two escape lines, two bump pads, and a photo-imageable dielectric layer on the mSAP patterned substrate.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: November 23, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Jaehyun Yeon, Suhyung Hwang, Hong Bok We, Kun Fang
  • Patent number: 11175014
    Abstract: An optoelectronically functional multilayer structure as well as related methods of manufacturing an optoelectronically functional multilayer structure are described herein.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: November 16, 2021
    Assignee: TACTOTEK OY
    Inventors: Juha-Matti Hintikka, Miikka Kärnä, Heikki Tuovinen, Tuomas Nieminen, Johannes Soutukorva, Ville Wallenius, Tero Rajaniemi, Tomi Simula, Jari Lihavainen, Mikko Heikkinen, Jarmo Sääski, Hasse Sinivaara, Antti Keränen, Ilpo Hänninen
  • Patent number: 11178761
    Abstract: A printed circuit board includes a printed circuit board includes a substrate portion having a recess portion and including a first circuit layer, abridge disposed in the recess portion and including an insulating layer and a bridge circuit layer, an insulating material disposed in at least a portion of the recess portion and covering at least a portion of the bridge, a second circuit layer disposed on the insulating material, and a first via penetrating through the insulating material and a portion of the bridge and connecting the second circuit layer and the bridge circuit layer to each other.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: November 16, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jung Hyun Cho, Kyung Hwan Ko, Chi Won Hwang
  • Patent number: 11177223
    Abstract: Disclosed is an apparatus and methods for making same. The apparatus includes a substrate, a set of electrical contacts disposed on the surface of the substrate, and an electromagnetic interference (EMI) shield pedestal structure, disposed between an outer periphery of the set of electrical contacts and an outer portion of the substrate.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: November 16, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Aniket Patil, Hong Bok We, Brigham Navaja
  • Patent number: 11178763
    Abstract: An electronic device according to one embodiment of the present disclosure can comprise: a housing including a front plate and a rear plate faced away from the front plate; a first printed circuit board arranged between the front plate and the rear plate; an electronic component arranged between the front plate and the rear plate and on a first plane that is substantially the same as the first printed circuit board; and a second printed circuit board for connecting the electronic component to the first printed circuit board, wherein the second printed circuit board comprises: a first terminal part parallel to the first plane and connected to the electronic component; a second terminal part parallel to the first terminal part and connected to the printed circuit board; a first planar part extending from the first terminal part toward the second terminal part and parallel to a second plane that is substantially orthogonal to the first plane; a second planar part extending from the second terminal part toward th
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: November 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seohoon Yang, Shihyun Kim, Juneyoung Hur
  • Patent number: 11178770
    Abstract: A semiconductor device, including an insulated circuit board that has a radiation plate, a resin board adhered to a front surface of the radiation plate, and a circuit pattern adhered to a front surface of the resin board. The resin board contains a resin. The semiconductor device further includes a wiring member, and at least one semiconductor chip, bonded to the front surface of the circuit pattern or electrically connected to the wiring member. The circuit pattern has at least one pair of side portions opposite to each other that are supported by the resin board.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: November 16, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hiroki Kogawa
  • Patent number: 11172571
    Abstract: A multipiece element storage package of the present disclosure includes: a mother substrate which includes first element storage package regions, second element storage package regions, a dummy region, a first surface, and a second surface; a first stem electrode disposed in a part of the dummy region which part is in the first surface; and a second stem electrode disposed on the second surface. The first element storage package regions and the second element storage package regions each include a frame body disposed on the first surface, a first wiring conductor disposed on the first surface, and including one end located inside the frame body and the other end connected to the first stem electrode, and a second wiring conductor including one end which is located on the first surface and inside the frame body and the other end which is connected to the second stem electrode.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: November 9, 2021
    Assignee: KYOCERA Corporation
    Inventors: Daisuke Ueyama, Chiaki Doumoto
  • Patent number: 11165247
    Abstract: A protection circuit and a printed circuit board (PCB) for a terminal camera includes, in a configuration for coupling with a voice control motor (VCM), a drive circuit, a first circuit, a second circuit, a first protection system, a second protection system, and a third protection system. The first circuit and the second circuit are choke inductors or choke circuits including choke inductors, and are configured to couple to two ends of the VCM. The first protection system, the second protection system, and the third protection system are coupled to other key positions of the circuits. The devices are arranged on a top layer of the PCB, and a plurality of layers of the PCB are configured to route a signal based on design requirements.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: November 2, 2021
    Assignee: HONOR DEVICE CO., LTD.
    Inventors: Bo Xu, Chao Wang, Jie Dong, Yi Wang, Qiao Sun, Zhiyong Sun
  • Patent number: 11166374
    Abstract: An electronic device includes a first circuit board, a second circuit board stacked with the first circuit board, and a connection plate connected between the first circuit board and the second circuit board. The connection plate includes a signal transmission part and at least one ground part at a spacing to the signal transmission part. The ground part can be used as a reference ground for a signal transmitted by the signal transmission part, so that the characteristic impedance of the signal transmission part is controllable, and the signal transmitted by the signal transmission part has strong continuity, thereby maintaining good matching performance and reducing an insertion loss caused by characteristic impedance mismatch.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: November 2, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Hui Wang, Dan Qiu, Zhijun Chen, Daiping Tang
  • Patent number: 11165231
    Abstract: An electrical box for accommodating at least one duplex electrical outlet including a first side, a second side having a mount opening therein. The electrical box also includes a mounting tube. The mounting tube is mountable to the mount opening. The mounting tube further includes first tubular member having a first length, and a second member fittable within the first tubular member. The second member further includes a tubular main body including a tubular portion fittable within the first tubular member, and a first end including a stop. The first end and stop engage the mount opening in the second side.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: November 2, 2021
    Inventor: Glenn Liubakka
  • Patent number: 11160165
    Abstract: A component carrier and a method of manufacturing a component carrier are provided. The component carrier includes a stack having a front side and a back side, the stack including a plurality of stacked electrically insulating layer structures, a through hole being narrower in its inner portion compared to its exterior portions and extending through the plurality of electrically insulating layer structures so that sidewalls of each of the electrically insulating layer structures delimit respective parts of the through hole, and an electrically conductive filling medium filling at least a part of the through hole.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: October 26, 2021
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Mikael Tuominen, Seok Kim Tay, Sally Sun, Robin Zhang
  • Patent number: 11158437
    Abstract: The invention relates to a cable comprising at least one electrically insulating layer obtained from a polymer composition comprising at least one polypropylene-based thermoplastic polymer material and at least one inorganic filler chosen from silicates, boron nitride, carbonates, and a mixture thereof, and to a process for preparing said cable.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: October 26, 2021
    Assignee: NEXANS
    Inventors: Gabriele Perego, Christelle Mazel, Dimitri Charrier, Daphné Merle
  • Patent number: 11153969
    Abstract: A flexible display panel and a display device are provided. The flexible display panel includes a bent portion. The bent portion includes a substrate layer group and a conductive wire group. The conductive wire group is located on the substrate layer group. The conductive wire group includes a plurality of conductive wires in a curved shape. At least two of the plurality of conductive wires cross and surround at least one closed region. The at least one closed region is provided at least corresponding to a bent region of the bent portion.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: October 19, 2021
    Assignee: Yungu (Gu'an) Technology Co., Ltd.
    Inventor: Li Lin
  • Patent number: 11139234
    Abstract: A package carrier includes a substrate, at least one interposer disposed in at least one opening of the substrate, a conductive structure layer, a first build-up structure, and a second build-up structure. The interposer includes a glass substrate, at least one conductive via, at least one first pad, and at least one second pad. The conductive via passes through the glass substrate, and the first and the second pads are disposed respectively on an upper surface and a lower surface of the glass substrate opposite to each other and are connected to opposite ends of the conductive via. The conductive structure layer is disposed on the substrate and is structurally and electrically connected to the first and the second pads. The first and the second build-up structures are disposed respectively on the first and the second surfaces of the substrate and are electrically connected to the conductive structure layer.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: October 5, 2021
    Assignee: Unimicron Technology Corp.
    Inventors: Wei-Ti Lin, Chun-Hsien Chien, Yu-Hua Chen