Abstract: A semiconductor device includes a gate electrode and a gate dielectric. The gate electrode extends from a first surface of a silicon carbide body into the silicon carbide body. The gate dielectric is between the gate electrode and the silicon carbide body. The gate electrode includes a metal structure and a semiconductor layer between the metal structure and the gate dielectric.

Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.

Abstract: A multichip module provided with a first substrate, a first semiconductor chip, a second substrate and a third substrate. The first semiconductor chip has a first surface provided with a first electrode and a second surface mounted on the first substrate so that the first wiring of a first mount surface of the first substrate is electrically connected to the first electrode. The second substrate has a second mounting surface and a third mounting surface bonded to the first substrate so that the second mounting surface is opposed to the first mounting surface. The third substrate has a fourth mounting surface provided with a second wiring and a fifth mounting surface bonded to the second silicon substrate so that the fourth mounting surface is opposed to the third mounting surface and is mounted with the first semiconductor chip so that the second wiring is electrically connected to the second surface.

Abstract: A vertical SiC MOSFET having a source terminal, a drain terminal, and a gate region, as well as an epitaxial layer disposed between the source terminal and the drain terminal and having a doping of a first type, is furnished, a horizontally extending intermediate layer, which has regions having a doping of a second type different from the doping of a first type, being embedded into the epitaxial layer. The vertical SiC MOSFET is notable for the fact that at least the regions having doping of a second type are electrically conductively connected to the source terminal. The gate region can be disposed in a gate trench.

Abstract: A method of forming a semiconductor device and resulting structures having an etch-resistant interlayer dielectric (ILD) that maintains height during a top epitaxy clean by forming a dielectric layer on a semiconductor structure; wherein the dielectric layer includes a first dielectric material; converting at least a portion of the dielectric layer to a second dielectric material; and exposing the portion of the dielectric layer to an etch material; wherein the etch material includes a first etch characteristic defining a first rate at which the etch material etches the first dielectric material; and wherein the etch material further includes a second etch characteristic defining a second rate at which the etch material etches the portion of the dielectric layer; wherein the first rate is different than the second rate.

Abstract: An FET comprises a source, a drain, a channel, and a gate encompassing the channel. The channel has a first region that is thinner than in a second region. The Threshold Voltage, Vth, is larger in the first region than in the second region causing an asymmetric Vth across the length of the channel. Modeling has shown that the Vth increases along the channel from about 50 milliVolts (mV) for N-FETs (about 55 mV for a P-FETs) to about 125 mV for N-FETs (about 180 mV for P-FETs) as the channel width decreases from 4 nanometers (nm) to 2 nm.

Abstract: A method used in forming integrated circuitry comprises forming conductive line structures having conductive vias laterally between and spaced longitudinally along immediately-adjacent of the conductive line structures. First insulating material is formed laterally between immediately-adjacent of the conductive vias, Second insulating material is formed directly above the first insulating material and directly above the conductive vias. The second insulating material comprises silicon, carbon, nitrogen, and hydrogen. A third material is formed directly above the second insulating material. The third material and the second insulating material comprise different compositions relative one another. The third material is removed from being directly above the second insulating material and the thickness of the second insulating material is reduced thereafter. A fourth insulating material is formed directly above the second insulating material of reduced thickness.

Abstract: A quantum dot includes a salt ligand at an outer surface thereof, the salt ligand including an anion and a cation, the cation having charge transporting properties. A light-emitting device includes an anode, a cathode, and an emissive layer disposed between the anode and the cathode, the emissive layer including multiple instances of the quantum dot. In some embodiments, the emissive layer is a crosslinked layer formed by depositing a mixture including the quantum dots on a layer, and subjecting at least a portion of the mixture to external activation stimuli to form the emissive layer including quantum dots dispersed in a crosslinked matrix.

Abstract: A method of fabricating a semiconductor device includes forming a device isolation layer in a substrate to define a plurality of active regions extending in a first direction; forming a trench in an upper portion of the substrate that crosses the active regions in a second direction that intersects the first direction; forming a sacrificial layer that fills the trench; forming support patterns on the sacrificial layer, wherein the support patterns fill recessed regions provided at a top surface of the sacrificial layer; and removing the sacrificial layer. The support patterns are spaced apart from each other with the active regions interposed therebetween.

Abstract: An embodiment of a semiconductor device includes a plurality of transistor sections separated from each other and a plurality of diode sections separated from each other. Each transistor section includes an emitter electrode and a collector electrode. Each diode section includes an anode electrode and a cathode electrode. Each transistor section is electrically coupled to a common gate pad. A ratio between an active transistor part and an active diode part of the semiconductor device is adjustable by activating a first number of the transistor sections by selectively contacting the emitter electrodes and the collector electrodes of the first number of transistor sections, and by activating a second number of the diode sections by selectively contacting the anode electrodes and the cathode electrodes of the second number of diode sections.

Abstract: Provided is a display device including a first sub-pixel, a second sub-pixel adjacent to the first sub-pixel. The first sub-pixel and the second sub-pixel each include a semiconductor film, a gate electrode, a gate insulating film, an interlayer insulating film, and a leveling film and further possesses a light-emitting element located over the leveling film. The display device has a partition wall located between the first sub-pixel and the second sub-pixel and a trench passing through the leveling film.

Abstract: Methods for depositing a gapfill dielectric film that may be utilized for multi-colored patterning processes are provided. In one implementation, a method for processing a substrate is provided. The method comprises filling the one or more features of a substrate with a dielectric material. The dielectric material is a doped silicate glass selected from borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), and borosilicate glass (BSG). The method further comprises treating the substrate with a high-pressure anneal in the presence of an oxidizer to heal seams within the dielectric material. The high-pressure anneal comprises supplying an oxygen-containing gas mixture on a substrate in a processing chamber, maintaining the oxygen-containing gas mixture in the processing chamber at a process pressure at greater than 2 bar and thermally annealing the dielectric material in the presence of the oxygen-containing gas mixture.

Abstract: A process is applied to develop a plurality of reverse conducting insulated gate bipolar transistors (RCIGBTs). The process comprises the steps of providing a wafer, applying a first grinding process, patterning a mask, applying an etching process, removing the mask, implanting N++ type dopant, applying a second grinding process forming a TAIKO ring, implanting P+ type dopant, annealing and depositing TiNiAg or TiNiVAg, removing the TAIKO ring, attaching a tape, and applying a singulation process. The mask can be a soft mask or a hard mask. The etching process can be a wet etching only; a wet etching followed by a dry etching; or a dry etching only.

Abstract: A method of fabricating a multi-color display includes dispensing a photo-curable fluid that includes a color conversion agent over a display having a backplane and an array of light emitting diodes electrically integrated with backplane circuitry of the backplane, activating a plurality of light emitting diodes in the array of light emitting diodes to illuminate and cure the first photo-curable fluid to form a color conversion layer over each of the first plurality of light emitting diodes to convert light from the plurality of light emitting diodes to light of a first color, and removing an uncured remainder of the first photo-curable fluid. This process is repeated with a fluid having different color conversion components for another color.

Abstract: Techniques for forming VTFET devices with tensile- and compressively-strained channels using dummy stressor materials are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer; forming bottom source and drains at a base of the fins; forming bottom spacers on the bottom source and drains; growing at least one dummy stressor material along sidewalls of the fins above the bottom spacers configured to induce strain in the fins; surrounding the fins with a rigid fill material; removing the at least one dummy stressor material to form gate trenches in the rigid fill material while maintaining the strain in the fins by the rigid fill material; forming replacement gate stacks in the gate trenches; forming top spacers on the replacement gate stacks; and forming top source and drains over the top spacers at tops of the fins. A VTFET device is also provided.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a base substrate; and a first doped epitaxial layer and a second doped epitaxial layer in the base substrate. Each of the first and second doped epitaxial layers is corresponding to a different gate structure on the base substrate. The semiconductor structure further includes a repaired dielectric layer formed on and surrounding each of the first and second doped epitaxial layer; a metal layer on the repaired dielectric layer; an interlayer dielectric layer over the base substrate and covering tops of gate structures; and a conductive plug on the metal layer and through the interlayer dielectric layer.

Abstract: A compound semiconductor device includes a compound semiconductor stack structure, a protective film provided on the compound semiconductor stack structure and containing titanium oxide, and a polycrystalline diamond film provided on the protective film.

Abstract: Embodiments may also include a residual chemical reaction diagnostic device. The residual chemical reaction diagnostic device may include a substrate and a residual chemical reaction sensor formed on the substrate. In an embodiment, the residual chemical reaction sensor provides electrical outputs in response to the presence of residual chemical reactions. In an embodiment, the substrate is a device substrate, and the sensor is formed in a scribe line of the device substrate. In an alternative embodiment, the substrate is a process development substrate. In some embodiments, the residual chemical reaction sensor includes, a first probe pad, wherein a plurality of first arms extend out from the first probe pad, and a second probe pad, wherein a plurality of second arms extend out from the second probe pad and are interdigitated with the first arms.

Abstract: A substrate is provided having a top side and a bottom side, having redistribution layers therein, having at least one copper pillar connected to the redistribution layers on the top side and at least one copper pillar connected to the redistribution layers on the bottom side, and having at least one cavity extending partially into the bottom side of the substrate. At least one passive component is mounted onto the copper pillar on the top side and embedded in a molding compound. At least one silicon die is mounted in the cavity wherein electrical connections are made between the at least one silicon die and the at least one passive component through the redistribution layers. At least one solder ball is mounted on the at least one copper pillar on the bottom side of the substrate to provide package output.

Abstract: According to one embodiment, a semiconductor device includes a transistor having a diffusion layer extending along a surface of a substrate and a gate electrode arranged above the diffusion layer; and contacts having elongated bottom surfaces connected to the diffusion layer on both sides of the gate electrode, in which the contacts are arranged so that the bottom surfaces of the contacts are not aligned in a straight line with an extension direction of the diffusion layer.