Abstract: A delay cell includes a cascode transistor and an inverter. The cascode transistor is used to receive a control voltage to generate a bias current, and includes a source terminal, a drain terminal, and a gate terminal receiving the control voltage. The inverter is coupled to the cascode transistor and used to generate an output signal according to the bias current in response to an input signal.

Abstract: A divider and buffer circuit uses a receive command to initiate a reset of buffer circuitry prior to restarting to avoid a metastable state. For example, the divider and buffer circuit includes a first buffer circuit, a second buffer circuit, and a reset circuit. The reset circuit receives a command and provide a pulse on a reset signal in response to the command. In response to the reset pulse, the first buffer circuit provides a first divided clock signal having a first logical value based on respective logical values of received complementary clock signals and the second buffer circuit provides a second divided clock signal having a second logical value based on the respective logical values of the complementary clock signals. The command is a CAS SYNC command, in some examples.

Abstract: A pre-discharging based flip-flop having a negative setup time can include a flip-flop with an inverted output QN. The flip-flop includes a master section and a slave section. The master section latches a data input or a scan input signal based on a scan enable signal, and the slave section retains a previous value of the inverted output QN when a clock signal is at a low logic level. The master section retains a previously latched value of the data input or the scan input signal and the slave section fetches the latched value of the master section and provides a new inverted output QN when the clock signal is at a high logic level. Further, the master section includes sub-sections that are operated using a negative clock signal. An output of the master section is discharged to zero for a half of a phase of the clock cycle.

Abstract: This disclosure describes a charge pump circuit comprising a plurality of switches configured to control phases of the charge pump circuit for charging a first capacitor, a second capacitor and a third capacitor. The phases may include: a first phase that charges the first capacitor to a first voltage based on an input voltage; a second phase that charges the second capacitor to a second voltage based on the first voltage and the input voltage; a third phase that charges the first capacitor to a third voltage based on the input voltage; and a fourth phase that charges the third capacitor to a fourth voltage based the second voltage, the third voltage, and the input voltage. In some examples, one or more of the capacitors are charged with duty cycles that are less than 50 percent.

Abstract: High power radio frequency (RF) switches with low leakage current and low insertion loss are provided. In one embodiment, an RF switch includes a plurality of terminals including an antenna terminal, a receive terminal, and a transmit terminal. The RF switch also includes a plurality of transistors that are controllable to set the RF switch in a first mode or a second mode, and an inductor electrically connected between the antenna terminal and the receive terminal.

Abstract: A waveform shaping circuit is configured without including a diode that is affected by temperature. The waveform shaping circuit includes: a capacitor with one end into which a differential signal Vd0 is inputted and another end connected to an output; an impedance element that has one end connected to the other end of the capacitor and another end into which a target constant voltage is applied; a switch circuit that is constructed of a series circuit with an impedance element and a switch without including a diode, has one end connected to the output, and has another end into which the target constant voltage is applied; and a switch control circuit that shifts the switch into an on state during a low voltage period in an AC component of the differential signal and shifts the switch to an off state during a high voltage period of the AC component.

Abstract: According to the present embodiment, a semiconductor integrated circuit is a semiconductor integrated circuit that drives a switching element including a first field-effect transistor and a second field-effect transistor connected to the first field-effect transistor in anti-series, and includes a driving circuit and a control circuit. The driving circuit turns on or off the first and second field-effect transistors. The control circuit controls the driving circuit in accordance with a control signal input from one signal input terminal.

Abstract: Disclosed is an electronic device, which includes an amplifier circuit that receives a feedback voltage and a reference voltage and amplifies a difference between the feedback voltage and the reference voltage to output an amplified difference voltage, an analog-to-digital converter that converts the amplified difference voltage to a digital code including two or more bits, and low-dropout (LDO) regulators that outputs output voltages based on the digital code. Each of the LDO regulators includes power transistors outputting a corresponding output voltage of the output voltages, drives one of the power transistors in a switching state, and drives each of remaining power transistors in a turned-on state or a turned-off state.

Abstract: A method for operating a clock product includes selectively coupling a first output divider and a second output divider based on a determination of whether the first divider value is integrally related to the second divider value. In response to the first divider value being integrally related to the second divider value, the selectively coupling includes cascading the first output divider with the second output divider. In in response to the first divider value being non-integrally related to the second divider value, the selectively coupling includes configuring the second output divider to be cascaded with a first phase-locked loop and in parallel with the first output divider and to be responsive to an error correction signal based on a difference in response times of the first output divider and the second output divider to a change in a filtered phase difference signal of the first phase-locked loop.

Abstract: A waveform generator configured to generate two waveforms of opposite polarity so as to provide a voltage gain across a load. The waveform generator has a primary side circuit comprising a first inductor. The waveform generator has a secondary side circuit comprising a second inductor, a first output region conductively coupled to the load, and a second output region conductively coupled to the load. The second inductor is inductively coupled to the first inductor. The first inductor is conductively coupled to the first output region so as to supply a first of the two waveforms to the load. The second inductor is conductively coupled to the second output region so as to supply a second of the two waveforms to the load. A system incorporating the waveform generator and a method of driving the waveform generator are also provided.

Abstract: Duty signal ratio and signal generation circuits with clock signal duty ratio stabilization under decreased power supply conditions are disclosed. In one example, a duty ratio correction circuit includes an inverting buffer, a capacitor, a low pass filter, an error amplifier, and an adjusting unit. The capacitor adjusts the rising and falling times of an inverted signal output from the inverting buffer. The low pass filter extracts a low frequency component of the inverted signal. The error amplifier adjusts a duty ratio of the inverted signal by controlling at least one of an output source current and an output sink current of the inverting buffer on the basis of a difference between the extracted low frequency component and a reference signal. The adjusting unit adjusts the control of the inverting buffer by the error amplifier.

Abstract: A charge pump circuit arrangement includes a multitude of capacitors of a first and a second group controlled by non-overlapping clock pulses. The capacitors are partly realized in a semiconductor substrate including a deep well doping region and a high voltage doping region surrounded by the deep well doping region. Switches are connected to a pair of capacitors to control the deep well doping regions with signals in phase with the corresponding clock signal.

Abstract: An electronic device is provided. A buffer circuit, having improved reliability according to the present disclosure, includes a pause detector and an output signal controller. The pause detector receives an input signal and generates a pause signal which indicates whether the input signal is in a toggle state or a pause state. The output signal controller generates an output signal based on the input signal and controls a duty cycle of the output signal according to the pause signal.

Abstract: A switching power conversion circuit includes a conversion capacitor, a capacitive power conversion circuit, an inductor, an inductive power conversion circuit and a switching control circuit. The capacitive power conversion circuit includes plural switching devices for generating an intermediate voltage which is in a predetermined proportional relationship to the input voltage. The inductive power conversion circuit includes plural switching devices for converting the intermediate voltage to an output voltage. The plural switching devices of the capacitive power conversion circuit and the inductive power conversion circuit switch the conversion capacitor and the inductor periodically according to the duty ratio of the switching control signal generated by the switching control circuit. The capacitive power conversion circuit and the inductive power conversion circuit share one of the plural switching devices.

Abstract: A driving apparatus including: gate driving circuit to drive gates of a first semiconductor element and a second semiconductor element connected in series between a positive side power supply line and a negative side power supply line; a first timing generating circuit to generate a first timing signal when voltage applied to the second semiconductor element becomes reference voltage during a turn-off period of the first semiconductor element; and a first driving condition change circuit, wherein the gate driving circuit relaxes change in a charge amount of the gate of the first semiconductor element, according to the first timing signal.

Abstract: A switched-capacitor DC-DC voltage converter and a control method thereof. The switched-capacitor DC-DC voltage converter comprises at least one switch array, comprising a capacitor and at least one switch group, wherein the switch group comprises a plurality of power switches connected to one another in parallel, and one end of the capacitor is electrically connected to the switch group; and a control circuit, converting an input control signal into a control signal set, and outputting the control signal set to the switch group, and the control signal set comprises a plurality of control signals with phase delayed sequentially and the duty cycle reduced sequentially.

Abstract: A system may include an output driving stage comprising a first switch configured to selectively open and close an electrical path between a first supply voltage and an output terminal of the output driving stage and a second switch configured to selectively open and close an electrical path between a second supply voltage and the output terminal of the output driving stage, wherein the second supply voltage is lower than the first supply voltage. The system may also include detection and protection circuitry configured to monitor a physical quantity indicative of the second supply voltage and responsive to the physical quantity exceeding an overvoltage threshold, electrically isolate the output terminal from the second supply voltage.

Abstract: A voltage converter circuit may include: a first input node; a second input node; a first output node; a second output node; one or more charge pumps that convert a first input voltage supplied to the first input node up to a first output voltage and convert a second input voltage supplied to the second input node down to a second output voltage; and a control circuit to control the one or more charge pumps according to two operational modes. In the first operation mode, the control circuit supplies the first input voltage to the first input node, leaves the second input node floating, and outputs the first output voltage at the first output node. In the second operation mode, the control circuit supplies the second input voltage to the second input node, leaves the first input node floating, and outputs the second output voltage at the second output node.

Abstract: A conversion circuit includes a main device and a voltage control switching circuit. The voltage control switching circuit includes a first terminal configured to receive an original signal, a second terminal coupled to the control terminal of the main device and configured to transmit a driving signal to drive the main device, and a reference terminal coupled to the second terminal of the main device. A voltage level of the driving signal is generated by the voltage control switching circuit. The voltage control switching circuit further includes a first voltage-control switch. The first drain terminal of the voltage-control switch is coupled to the first terminal. The first source terminal of the voltage-control switch is coupled to the second terminal. The first gate terminal of the voltage-control switch is coupled to the reference terminal.

Abstract: Techniques are provided for phase coherent frequency synthesis. An embodiment includes a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to produce a first digital phase signal representing phase data corresponding to phase points on a first sinusoidal waveform. The embodiment also includes a second phase accumulator to produce an incrementing reference count at the clocked rate and multiply it by the FCW to produce a second digital phase signal representing phase data corresponding to phase points on a second sinusoidal waveform. The multiplication is performed in response to change in the FCW. The embodiment further includes a multiplexer to select between the first and second digital phase signals based on completion of the multiplication. The embodiment also includes a phase-to-amplitude converter to generate digital amplitude data corresponding to the phase points on a sinusoidal waveform associated with the selected digital phase signal.