Abstract: Techniques are provided for phase coherent frequency synthesis. An embodiment includes a first phase accumulator to accumulate a frequency control word (FCW) at a clocked rate to produce a first digital phase signal representing phase data corresponding to phase points on a first sinusoidal waveform. The embodiment also includes a second phase accumulator to produce an incrementing reference count at the clocked rate and multiply it by the FCW to produce a second digital phase signal representing phase data corresponding to phase points on a second sinusoidal waveform. The multiplication is performed in response to change in the FCW. The embodiment further includes a multiplexer to select between the first and second digital phase signals based on completion of the multiplication. The embodiment also includes a phase-to-amplitude converter to generate digital amplitude data corresponding to the phase points on a sinusoidal waveform associated with the selected digital phase signal.

Abstract: An apparatus for generating a substantially constant DC reference voltage. The apparatus includes a reference voltage generator configured to generate a substantially constant direct current (DC) reference voltage based on a voltage on a data signal transmission line, wherein the voltage is based on a bandgap reference voltage. In one implementation, the data signal transmission line is a differential signal transmission line and the voltage is a common mode voltage. In another implementation, the data signal transmission line is an I-data signal transmission line and a Q-data signal transmission line, and the voltage is an average or weighted-average of the common mode voltages of the I- and Q-differential signals. In another implementation, the reference voltage is based on a single-ended (e.g., positive- and/or negative)-component or vice-versa of I- and Q-data signals, respectively.

Abstract: A multiplexing latch circuit includes first, second, and third tristate inverters and an inverter. The first tristate inverter includes an output terminal and an input terminal coupled to a first data line, the second tristate inverter includes an output terminal and an input terminal coupled to a second data line, and the third tristate inverter includes an input terminal and an output terminal. The first inverter includes an input terminal coupled to the output terminals of each of the first, second, and third tristate inverters, an output terminal coupled to the input terminal of the third tristate inverter, and is configured to generate an output signal based on data received on one of the first data line or the second data line.

Abstract: A clock circuit includes a set of level shifters, a duty cycle adjustment circuit and a calibration circuit. The set of level shifters is configured to output a first set of phase clock signals having a first duty cycle. The duty cycle adjustment circuit is configured to generate a first clock output signal responsive to a first phase clock signal, a second phase clock signal and a set of control signals, and adjust the second duty cycle responsive to the set of control signals or a phase difference between the first phase clock signal and the second phase clock signal. The calibration circuit is configured to perform a duty cycle calibration of a second duty cycle of the first clock output signal based on an input duty cycle, and to generate the set of control signals responsive to the duty cycle calibration.

Abstract: A switching element control circuit: a third electrode voltage control part; a temperature detection part; a first electrode current detection part; a memory part which stores information including an initial threshold voltage and an operation temperature/first electrode current characteristic of the threshold voltage; and a threshold voltage calculation part which calculates a threshold voltage at the time of operating the switching element based on information including the initial threshold voltage, the operation temperature of the switching element, and a first electrode current, and information relating to an operation temperature/first electrode current characteristic of a threshold voltage, wherein the third electrode voltage control part controls the third electrode voltage based on a threshold voltage at the time of operating the switching element calculated by the threshold voltage calculation part.

Abstract: Disclosed is an electronic device. The electronic device includes an input node, an output node, a power node that transfers a voltage of a third level to the output node when a voltage of the input node is a first level, and a capacitor that transfers a change in the voltage of the input node to the output node through a coupling such that a voltage of the output node is adjusted to a fourth level, when the voltage of the input node changes from the first level to a second level.

Abstract: Embodiments of a digital step attenuator are disclosed. In an embodiment, a digital step attenuator includes a radio frequency (RF) input, an RF output, an attenuation circuit connected between the RF input and the RF output, a shunt switching circuit connected to the attenuator circuit, and a bypass switching circuit connected between the RF input and the RF output. The bypass switching circuit includes a first bypass transistor, and a second bypass transistor, wherein the first bypass transistor and the second bypass transistor are series connected to each other between the RF input and the RF output, and a bypass shunt transistor connected between the first bypass transistor and the second bypass transistor.

Abstract: A variable gain phase shifter includes an I/Q generator and a vector summation circuit. The I/Q generator generates phase signals based on an input signal. The vector summation circuit adjusts magnitudes and directions of first, second, third and fourth in-phase vectors and first, second, third and fourth quadrature vectors, and generates an output signal by summing the in-phase vectors and the quadrature vectors, based on the phase signals, selection signals and current control signals. The vector summation circuit includes first, second, third and fourth vector summation cells and first, second, third and fourth current control circuits. The first and second vector summation cells adjust the directions of the first and second in-phase vectors and the first and second quadrature vectors. The third and fourth vector summation cells adjust the directions of the third and fourth in-phase vectors and the third and fourth quadrature vectors.

Abstract: An electronic device is provided. A buffer circuit, performing an optimized operation according to the present disclosure, includes a pause detector, a toggle detector, and an output signal controller. The pause detector receives an input signal and generates a pause signal which indicates whether the input signal is in a pause state. The toggle detector receives the input signal and the pause signal and generates a toggle signal which indicates whether the input signal is in a toggle state. The output signal controller generates an output signal which controls input buffer circuits according to the toggle signal.

Abstract: An apparatus for regulating a supply voltage supplied from a voltage source to a load via a supply line is provided. The apparatus includes a control circuit configured to generate a control signal based on a difference between a value of the supply voltage and a nominal value of the supply voltage. Further, the apparatus includes a switch circuit configured to couple a charged capacitive element to the supply line based on the control signal.

Abstract: A semiconductor device includes a circuit including an input coupled to a first node; and a first signal control circuit configured to determine a voltage of the first node in a low power mode, wherein the first signal control circuit sets a voltage of the first node to a first value in an n-th occurrence of the low power mode and a second value different from the first value in an m-th occurrence of the low power mode, and wherein n and m are two different natural numbers.

Abstract: A semiconductor device according to embodiments includes a normally-off transistor having a first electrode, a second electrode, and a first control electrode, a normally-on transistor having a third electrode electrically connected to the second electrode, a fourth electrode, and a second control electrode, a first element having a first end portion electrically connected to the first control electrode and a second end portion electrically connected to the first electrode, and the first element including a first capacitance component; and, a second element having a third end portion electrically connected to the first control electrode and the first end portion and a fourth end portion, and the second element including a second capacitance component, wherein, when a threshold voltage of the normally-off transistor is denoted by Vth, a maximum rated gate voltage of the normally-off transistor is denoted by Vg_max, a voltage of the fourth end portion is denoted by Vg_on, the first capacitance component is deno

Abstract: A switched-capacitor power converting apparatus and an operating method thereof are disclosed. The switched-capacitor power converting apparatus includes an output stage, a determination circuit, a switch control circuit and a voltage regulation circuit. The output stage has an output terminal. The determination circuit is coupled to the output terminal, and generates a mode switching signal according to an output voltage of the output terminal and a reference voltage. The switch control circuit is coupled to the output stage and the determination circuit and controls the output stage to operate in a default voltage mode or an operation mode according to the mode switching signal. The voltage regulation circuit is coupled to the output terminal and the determination circuit and maintains the output voltage of the output terminal at a default value in the default voltage mode.

Abstract: According to one aspect, embodiments herein provide a power switching circuit, comprising a first terminal, a second terminal, a third terminal, and a plurality of switching devices, each switching device having a first transistor having a first gate, a first source, and a first drain, a second transistor having a second gate, a second source, a second drain coupled to the first source, and a bipolar body diode coupled between the second drain and the second source, and a unipolar diode configured to prevent a transition voltage applied across the first gate and the first source from exceeding a degradation threshold of the first transistor during a transition period, wherein a first switching device of the plurality of switching devices is coupled between the first and third terminals and the and a second switching device of the plurality of switching devices is coupled between the second and third terminals.

Abstract: The present disclosure provides a power transistor driving method, a driving circuit and a switching circuit. When the power transistor is an N-type component, a driving pole of the power transistor is pulled down in a first current, and when a time period recorded by the timer reaches a first time period, a pull-down switch is turned on or the driving pole of the power transistor is pulled down in a second current; the driving pole of the power transistor is pulled down by the pull-down switch; when a timer is started from a moment at which the power transistor is turned off, the first time period is higher than a time period from a moment at which a switching tube is turned off to a moment at which the change rate of the drain-source voltage of the power transistor along with the time is higher than the first slope.

Abstract: In one embodiment, a phase lock loop circuit includes a control circuit, wherein the control circuit is configured to input an estimation having a second frequency and a second phase. The second frequency is selected from a range of frequencies including a first frequency from an acquired signal. A numerically controlled oscillator is coupled to the control circuit, wherein the control circuit is configured to control an output response of the numerically controlled oscillator. The numerically controlled oscillator is configured to receive the estimation from the control circuit and generate an output signal in response to the estimation. A phase detector is coupled to the control circuit and the numerically controlled oscillator, wherein the phase detector is configured to compare the first signal and the output signal and produce a comparison output, the comparison output indicative of a phase difference between the first signal and the estimation.

Abstract: A flying DC-to-DC converter has a capacitor protection function of preventing a flying capacitor from overheating. The flying DC-to-DC converter estimates the temperature of a capacitor on the basis of a switching duty and an inductor current determined according to a result of comparison between an output voltage and a voltage instruction value, and determines whether to perform de-rating.

Abstract: A power transmission device is provided that enables more accurate detection of an undesired switching state for a switching element and an appropriate supply of power. The power transmission device includes a power supply, a switching element, a ringing detection circuit, and a control circuit unit. The ringing detection circuit detects ringing that occurs in the switching element. The control circuit unit controls at least the power supply or the switching element in accordance with a detection result of the ringing detection circuit. The ringing detection circuit includes a diode and a resistor. The diode conducts when a negative polarity voltage is generated in the switching element. The resistor is connected in series with the diode.

Abstract: A switching regulator having a low start-up voltage includes a power stage and a switch control circuit. The switch control circuit includes a power control switch. The power control switch is formed by a low threshold voltage transistor having a first conductivity type in a semiconductor substrate. The low threshold voltage transistor having the first conductivity type includes a first lightly doped region having a second conductivity type which forms a channel region of the low threshold voltage transistor having the first conductivity type. The semiconductor substrate includes a second lightly doped region having the second conductivity type which is formed by a same manufacturing process as the first lightly doped region having the second conductivity type. The second lightly doped region having the second conductivity type forms adrift region of a high-voltage transistor having the second conductivity type in the semiconductor substrate.

Abstract: A semiconductor device includes a test clock generation circuit, a test data generation circuit, and a control code generation circuit. The test clock generation circuit delays a clock signal based on a delay selection signal in a test mode to generate a test clock signal. The test data generation circuit delays data to generate test data. The control code generation circuit latches the test data based on the delay selection signal and the test clock signal to generate a control code.