Abstract: A tester is connected to a signal output terminal provided in a DRAM chip, and a frequency of a clock signal output from an internal timer is monitored. The frequency of the clock signal is varied by changing the combination of 3 bit signals, so as to obtain signals by which the frequency closest to the set value is obtained. A fuse in the internal timer is disconnected to set the frequency of the clock signal so as to obtain the same state as in the case where that signal is applied. The internal timer includes an oscillator formed of a plurality of inverters connected in ring shape and a variable capacitance circuit for each inverter. Each variable capacitance circuit includes a plurality of sets of transfer gates, fuses and capacitors connected between the output node of the corresponding inverter and a prescribed potential line.

Abstract: An oscillator circuit includes an oscillation circuit producing a RAMP signal and at least two control signals STATE2 and STATE3, and a comparator comparing an externally produced error signal ERR with the RAMP signal. When the ERR signal is between minimum and maximum levels of the RAMP signal, the duty cycle of a PWMOUT signal of the oscillator circuit varies as a function of the difference between the ERR and RAMP signals, and preferably accounts for approximately 85% of the total period. When the ERR signal is less than or equal to the minimum level of the RAMP signal, the duty cycle of the PWMOUT signal is fixed at a first value which is preferably approximately 5% of the total duty cycle. When the ERR signal is greater than or equal to the maximum level of the RAMP signal, the duty cycle of the PWMOUT signal is fixed at a second value which is preferably approximately 90% of the total period.

Abstract: A frequency detector embodying the invention includes circuitry for comparing first (e.g., a reference) and second (e.g., a recovery clock) signals having first and second frequencies, respectively, and for producing an output signal having: (a) a first condition characterized as a “dead zone” when their frequency difference is within a predetermined frequency range; (b) a second condition when the frequency of the first signal is greater than that of the second signal by the predetermined range; and (c) a third condition when the frequency of the second signal is greater than that of the first by the predetermined range. Frequency detectors embodying the invention are suitable for use in frequency tuning systems.

Abstract: An integrated circuit includes a ring oscillator with a frequency stabilizing circuit. The frequency stabilizing circuit produces compensated voltage signals in response to changes in supply voltage and temperature to modify the conductances of field-effect transistors of the frequency stabilizing circuit to compensate the conductive path of the discharge current of a capacitor from the ring oscillator in order to stabilize the oscillation frequency.

Abstract: A clock recovery system includes a source of a data signal, and a free-running frequency adjustment circuit. The free-running frequency adjustment circuit includes an injection-locked oscillator having a free-running frequency and generating a clock signal and a phase locked loop, coupled in parallel with the injection locked oscillator, and generating a control signal adjusting the free running frequency of the injection locked oscillator.

Abstract: In a frequency detection method for adjusting a clock signal frequency to the data rate of a received data signal, the clock signal which is predivided by a factor of 4. The predivided clock signal and the received data signal are each frequency-divided by the same division factor. The frequencies of the two frequency-divided signals are then determined by counting processes and are compared by a subtractor. The frequency difference that is determined is then converted into an analog output signal for controlling the clock signal frequency. This method can be applied in the transmission of data.

Abstract: A digital data modulator includes a source of a plurality of digital data signals having a common data bit period. A plurality of encoders each encode a corresponding one of the plurality of digital data signals using a variable pulse width code having edges occurring in respective non-overlapping intervals within the data bit period. A plurality of pulse signal generators each generate respective pulses representing the edges of the corresponding one of the encoded plurality of digital data signals. A carrier signal generator generates a carrier signal having carrier pulses corresponding to the respective pulses.

Abstract: An orthogonal modulator capable of eliminating an offset component between an I signal and a Q signal. The orthogonal modulator includes a generation circuit for generating a plurality of base band signals such as voice signal, a mixing circuit for mixing the base band signals and a plurality of carrier waves, an extraction circuit for extracting each DC offset component generated by the generation circuit or the mixing circuit, a comparison circuit for comparing the DC offset components thus extracted with each other, an addition circuit for adding a plurality of comparison results with other comparison results, and an offset elimination circuit for eliminating the DC offset components included in a plurality of addition signals by subtracting the DC offset components from the base band signals before they are applied to the mixing circuit.

Abstract: A frequency synthesizer that can accurately compensate for ripple current. The frequency synthesizer 1 having a PLL loop containing an oscillator 31 and a charge pump circuit 35 has a detector circuit 40 and a delay circuit 39. The detector circuit 40, by detecting a ripple current with a superimposed compensating current, detects the time difference between the output time of the compensating current and the output time of the ripple current, and since the delay circuit 39 delays one or both of the output time of the compensating current and the output time of the ripple current based on that detection result, the time difference for the output times can be made small, and if a compensating current is supplied that is equal to the ripple current, it becomes possible to accurately remove the ripple current.

Abstract: Methods and systems are disclosed for eliminating a phase transient of a controlled frequency oscillator, caused by replacing a first reference signal by a second reference signal when the first reference signal becomes corrupted or otherwise unavailable, and for running a controlled frequency oscillator in a frequency-controlled holdover mode. The contradictory requirements of using a relatively low-cost controlled frequency oscillator tunable over a relatively wide frequency range and achieving high stability of its frequency in holdover mode are satisfied.

Abstract: A demodulator circuit including: a signal generating circuit for generating a sine-wave signal and a cosine-wave signal whose frequencies are same as that of the carrier wave of a modulated signal, a multiplying circuit for multiplying the modulated signal by the sine-wave signal and the cosine-wave signal generated by the signal generating circuit, and a filtering circuit for eliminating the frequency twice as high as that of the carrier wave from each of the results of the computation conducted by the multiplying circuit. Due to this, no restriction is imposed by the frequency of the system clock signal in configuring the system as a whole.

Abstract: A stage for a voltage controlled oscillator includes a first p-channel transistor having a gate defining a control node, having a source adapted to be coupled to a supply voltage, and having a drain; a second p-channel transistor having a gate coupled to the control node, having a source coupled to the supply voltage, and having a drain; a first n-channel transistor having a gate defining a first input, having a drain coupled to the drain of the first p-channel transistor and defining a first node, and having a source; a second n-channel transistor having a gate defining a second input, having a drain coupled to the drain of the second p-channel transistor and defining a second node, and having a source; a current draw; first and second loads; a first source follower having an input coupled to the first node; and a second source follower.

Abstract: An apparatus and method for achieving accurate temperature-invariant sampling frequencies in a device, such as, a multiple message non-volatile multilevel analog signal recording and playback system is described. An oscillator is used to generate an oscillation frequency. A bandgap voltage generator generates a zero temperature coefficient voltage reference (V(OTC)) that is independent of temperature. This V(OTC) is applied to the oscillator. A variable temperature coefficient voltage (V(TC)) that compensates for temperature coefficient variations of a resistor to which V(TC) is applied produces a stable oscillator current Iosc. Therefore, the stable oscillator current Iosc is likewise independent of the temperature coefficient variations of the resistor. The stable oscillator current Iosc is applied to the oscillator such that the oscillator generates a stable temperature-invariant oscillation frequency.

Abstract: A Voltage Controlled Oscillator (VCO) with the ability to tune its operating frequency over a wide range using a limited control voltage range. The VCO implements a novel resonant circuit that provides the wide frequency tuning range and simultaneously provides increased immunity to induced low frequency noise. The resonant circuit utilizes an element configuration that includes high pass filters on each input to the resonant circuit. Varactor diodes are used to couple a conventional tuning circuit to the remainder of the resonant circuit. This configuration allows the resonant frequency to tune over a wide range using a limited control voltage range.

Abstract: A variable-tuned type YIG oscillator accompanied with substantially no mechanical variations in the resonance circuit and a method of manufacturing the same are provided. An amplifier element, electrode, circuit pattern and others of the oscillator circuit portion of a YIG oscillator are integrated on the front face of a semiconductor substrate by the monolithic microwave integrated circuit manufacturing technique. A coupling loop is formed as a thick film conductor shaped so as to surround at least a portion of the outer periphery of a YIG crystal ball on the semiconductor substrate having the amplifier element, electrode, circuit pattern and others formed thereon. A hole for positioning a YIG crystal ball at a predetermined position inside of the coupling loop is formed in the semiconductor substrate from the front surface of the substrate, and the YIG crystal ball is fitted and fixed in the hole.

Abstract: A device and method capable of QPSK(Quadrature Phase Shift Keying) modulation, which up-converts a baseband signal to an IF(Intermediate frequency) signal. A phase compensator receives a digital I-signal (In-Phase signal) and a digital Q-signal (Quadrature-Phase signal) from a I/Q local signal forwarder. The phase compensator delays at least one of the received signals an amount necessary to realize a 90° phase difference between two baseband signals used to form a Quadrature Phase Shift Key output, effectively compensating for relative delays in the two baseband signals that would otherwise result in a phase difference that differs from the requisite 90° phase difference.

Abstract: An oscillator circuit having a first programmable divider for obtaining a reference signal by dividing the frequency of an oscillation signal of a piezoelectric resonator by a frequency dividing number, M. A PLL circuit using the reference signal as input thereto to obtain a multiplied signal, the multiplied signal being formed by multiplying the input signal by a second frequency dividing number N for a second programmable divider provided in a feedback circuit. A third programmable divider capable of dividing the frequency of the multiplied signal by a third frequency dividing number X and outputting the frequency-divided signal. The frequency dividing numbers M, N, and X can be set to values independent of each other. Therefore, innumerable combinations of the frequency dividing numbers M, N, and X can be used and the number of frequencies producible by one oscillator can be largely increased by enabling selection of any suitable one of such combinations.

Abstract: An oscillator circuit for use with a wire-loop inductive sensor and method for use. The oscillator circuit includes two balanced capacitors coupled to the wire-loop sensor, and an excitation circuit connectable with the capacitors at a selected polarity. Wherein, when the excitation circuit is connected to the capacitors, one of the capacitors is charged while the other capacitor is discharged, and both of the capacitors are discharged when the excitation circuit is disconnected to produce a pair of decaying oscillations having a caduceus-shaped output. The oscillator circuit highly attenuates common-mode noise detected by the wire-loop and differential noise from both ambient and crosstalk sources is filtered by active isolation.

Abstract: An improved low noise oscillator operates by periodically opening a ring oscillator to insert a reference input, thereby resetting any accumulated timing errors. The ring oscillator may be placed within the PLL to function as a voltage controlled oscillator. The loop in the ring oscillator is opened immediately prior to the arrival of the reference signal edge. While the ring oscillator loop is open, the reference signal is fed to the initial inverter instead of the initial inverter of the ring oscillator receiving the output from the last inverter of the ring oscillator. Shortly thereafter, the ring oscillator loop is closed again, and the structure operates as a conventional PLL with a ring oscillator until the next reset. The switching of the ring oscillator input is accomplished via a switch operable between a ring setting (loop back ring oscillator output) and a reset setting (reference signal as input).

Abstract: In a phase locked loop arrangement of a frequency synthesiser, a signal outputted from a voltage controlled oscillator is locked to a reference oscillator. A phase detector is arranged so that the frequency of the reference oscillator is a multiple of the frequency of the voltage controlled oscillator, which significantly reduces the phase noise emitted by the voltage controlled oscillator.