Abstract: An oscillator circuit having improved long term and short term phase stability. A source follower provides a signal to a bipolar transistor. The bipolar transistor is fed with a current from a current mirror which may be selectively controlled. A piezoelectric crystal and a high resistance element are connected in parallel from the collector of the bipolar transistor to the input of the source follower. The drive voltage to the piezoelectric crystal is controlled by the current mirror to improve long term frequency stability.

Abstract: A digital phase locked loop includes a digital phase detector which provides a magnitude control signal to adjust the step size of up and down adjustments in the phase/frequency of a digitally controlled oscillator, resulting in shorter lock-in or acquisition time and smaller jitter as compared to conventional digital phase locked loop devices. In the disclosed embodiments, the digital phase detector includes multiple bit shift registers in both the up and down directions to count or measure a number of up or down minimum width pulses and provide a pulse magnitude control based on the value of the shift registers to the digitally controlled oscillator. The digitally controlled oscillator includes a charge pump and voltage controlled oscillator. In one embodiment, the charge pump provides programmable control over its output current pulses to a capacitor which controls the output frequency of the voltage controlled oscillator.

Abstract: A wide-range and low power consumption voltage-controlled oscillator according to the invention includes a logic control circuit, a parallel series controllable inverter bank and a voltage control load. The logic control circuit consists of a plurality of logic gates for receiving a selecting signal from an external device and then transmitting a control signal. The parallel series controllable inverter bank consists of a plurality of series controllable inverter banks electrically connected in parallel for receiving the control signal and outputting an oscillation signal, wherein the control signal is used to control the number of the series controllable inverter banks electrically connected in parallel. The voltage control load is electrically connected between the parallel series controllable inverter bank and ground for serving as a load of the parallel series controllable inverter bank.

Abstract: A microwave/millimeter-wave integrated circuit (IC) realizes stable oscillation by reducing time-based variation of a load impedance. This IC connects an oscillator to an input terminal of a Lange coupler and connects to the isolation port of the Lange coupler a terminating resistor having a resistance equal to the load impedance connected to the output terminals of the Lange coupler. This connection stabilizes load impedance to the oscillator, and reduces variation in the oscillation frequency as a result of changes in load impedance.

Abstract: An oscillation circuit for outputting an oscillation signal includes a comparison circuit and a reference signal generation circuit. The comparison circuit compares two voltage levels and outputs a comparison result as the oscillation signal. The reference signal generation circuit provides a signal input to the comparison circuit. The reference signal generation circuit includes at least two resistance means coupled with each other in series, where one resistance means is given a smaller regulation of the resistance value relative to the temperature as compared with other resistance means.

Abstract: A receiver receives modulated message signals in non-coherent FSK and coherent 8PSK protocols. A selectively configurable processor demodulates the message signals, and includes a demodulator that derives in-phase and quadrature signals based on the message signals. A phase detector is responsive to the in-phase and quadrature signals and delayed in-phase and quadrature signals to derive a phase signal. A selector is responsive to the in-phase and quadrature signals to selectively connect a loop filter between the phase detector and the demodulator. When the selector connects the filter between the phase detector and demodulator, the demodulator is responsive to filtered phase signals to lock onto a frequency of the message signals so that the processor operates as a phase locked loop to demodulate coherent modulated signals.

Abstract: A microwave oscillator includes at least two active components and a dielectric resonator. The coupling between each active component and the dielectric resonator is of the transmission type and the inputs of neighboring active components are connected to a first point coupled to the resonator and likewise the outputs of the active components are connected to a second point coupled to the resonator. A push-push oscillator of the above kind is simple to produce and its operation is relatively insensitive to adjustments.

Abstract: There is a manufacturing limit on how small ceramic coaxial resonators can be produced, which leads to a limit on the frequency of resonance for these resonators. One technique to quadruple the effective frequency of a ceramic coaxial resonator is to couple four resonators into a ring configuration, each of the resonators having an electrical length of 90°. Further, each of the resonators has an amplifier coupled in parallel, these amplifiers having phase shifts approximately equal to 90° and further being controlled by a tuning voltage VTUNE. In operation, four oscillation signals are generated at the same frequency but out-of-phase by a factor of 90°. When combined, the resulting signal is an oscillation signal at four times the frequency of the original oscillation signals. At the same time, one of the oscillation signals used in the combination can be sampled and be used for feedback purposes within a PLL-FS.

Abstract: A quadrature demodulator capable of calibrating an I (Q) signal conversion section without stopping the receiving operation performed by the quadrature demodulator. The quadrature demodulator comprises: an adder 32 for generating a pseudo noise superimposed signal obtained by adding a user signal IF and a pseudo noise PN; a signal conversion section 100 for generating a converted signal obtained by mixing the pseudo noise superimposed signal with a local frequency signal L1 of a predetermined local frequency; a first multiplier 72 for generating a correlated signal obtained by multiplying the converted signal with the pseudo noise, a first integrator 82 for integrating the correlated signal to provide an output; and a succeeding circuit 90 for processing the converted signal in a desired way. While performing calibration by causing the first multiplier 72 to extract the pseudo noise, the quadrature demodulator allows the succeeding circuit 90 to process the converted signal in a desired way.

Abstract: A signal estimator estimates a transmission signal series using Viterbi algorithm, and outputs an estimated signal and a minimum path metric signal. A switching unit is controlled by a control signal in such a manner that, for a certain period from the start of the operation of PLL which requires quick response, a minimum path metric history signal is selected, while, in the other case, an estimated signal is selected. A replica generator generates a replica signal using a signal output from the switching unit. The generation of the replica signal using the path metric history signal offers quick response, but on the other hand, the accuracy is low. On the other hand, the use of the estimated signal offers high accuracy, but on the other hand, the response speed is low. Thus, a phase change contained in a received signal is corrected in a highly accurate and quick manner.

Abstract: A selectable oscillation circuit includes a first oscillation circuit, a second oscillation circuit, and a selector circuit. The selector circuit selectively switches on and off the first oscillation circuit and the second oscillation circuit, in accordance with the provision of a selector signal, to selectively switch between two communicating modes, with low-power consumption.

Abstract: A temperature compensating crystal oscillation device includes a constant voltage circuit (12) for outputting a predetermined voltage independent of the ambient temperature, a temperature sensor circuit (13) for outputting a voltage in proportion to the ambient temperature, and a control circuit (14) for receiving the constant voltage output from the constant voltage circuit (12) and the voltage output in proportion to the temperature from the temperature sensor circuit (13) and for generating a control voltage (Vc) used for compensating a temperature characteristic of a quartz oscillator in the entire range of the ambient temperature through polygonal lines approximation of a negative cubic curve by using continuous lines.

Abstract: The LC VCO includes an LC oscillator module with first and second tank nodes and a control module with positive and negative input voltage terminals. The control module includes four voltage dependent capacitive elements which are configured to be biased for operation as voltage dependent variable capacitances. The voltage dependent capacitive elements are interconnected such that the effect of a common mode input voltage is to increase the capacitance of two of the voltage dependent capacitive elements, while simultaneously decreasing the capacitance of two of the other voltage dependent capacitive elements by a substantially similar amount, such that a differential voltage applied across the positive and negative input voltage terminals is operable to change the capacitance of the voltage dependent capacitive elements, and thereby the frequency of the LC oscillator module, while effects on the output frequency of the oscillator caused by a common mode voltage tend to cancel.

Abstract: The phase locked loop (PLL) of the invention comprises a first divider (DIV1), a second divider (DIV2), a phase detection means (PFD) and an oscillator means (VCO) connected in a PLL loop configuration. The first divider (DIV1) and the second divider (DIV2) each have at least two different selectable frequency factors (a, b; c, d). A control means (CTPL) switches between pairs of frequency division factors selected respectively from both dividers (DIV1, DIV2) according to a predetermined switching pattern (Z). The usage of at least two different pairs of frequency division factors in the dividers (DIV1, DIV2) allows a high phase resolution, a fast tracking speed and a fine adjustment of the frequency/phase of the output signal of the voltage-controlled oscillator (VCO) in steps of ppm.

Abstract: A cost-effective continuous phase logic-based modulator and demodulator are provided to allow communications using binary frequency shift keying (BFSK) as well as M-ary FSK techniques. The modulator of the 1-bit precision modem architecture is based on a 1-bit precision numerically controlled oscillator (NCO), which provides complete programmability with respect to a frequency of the 1-bit precision logic-based modulator and/or demodulator. The output of the 1-bit precision NCO is upconverted to an intermediate frequency using a simple logic function, i.e., XNOR logic. The undesirable portion of the upconverted signal may be suppressed using I/Q image rejection, and/or an appropriate bandpass filter may be used. A band limited, hard limited signal at the high IF is presented to the 1-bit precision demodulator as a receive IF signal, which is treated as a 1-bit quantization of the signal. The receive IF signal is digitally down-converted to a low IF signal to produce an alias signal at the low IF frequency.

Abstract: A phase-locked loop (PLL) circuit having a shortened locking time. A first counter divides down the output from a reference signal source and produces output signal FR. A second counter divides down the output from a voltage-controlled oscillator (VCO) circuit and produces a second output signal FV. When the phase of the second output signal FV is lagging the phase of the first output signal FR, a control circuit resets the first counter. When the phase of the second output signal is leading the phase of the first output signal, the control circuit resets the second counter. As a result, the starting points of counting operations performed by the first and second counters are synchronized. This brings the phase difference detected by the phase comparator circuit into coincidence with the actual phase difference between the first and second output signals FR, FV. Thus, the phase difference is appropriately fed as a control voltage back to the VCO circuit thereby shortening the locking time.

Abstract: A voltage controlled oscillator (VCO) having a generally linear transfer characteristic across a wide frequency range of operation. The VCO is comprised of a voltage-to-current converter (V-I) and a current-controlled oscillator (ICO). A linearization of the output response of the VCO is accomplished by proper selection of the output responses of the V-I and ICO circuits, where the V-I portion is designed to have an inverse nonlinearity response as compared to the nonlinearity response of the ICO portion of the VCO. The combined effect is a linear response for the VCO. A nonlinear V-I characteristic can be achieved by adding several piecewise linear responses together to produce a combined nonlinear response.

Abstract: A differential LC-based voltage-controlled oscillator (LC-VCO), charge pump and loop filter architecture for providing improved noise immunity in integrated phase-locked loops (PLLs). A pair of voltage control signals are provided from a differential charge pump and loop filter architecture to respective voltage control inputs in the LC-VCO to differentially control the LC-VCO. The voltage control inputs are connected to respective terminals on opposite ends of a varactor tuning circuit. The differential voltage applied across the varactor tuning circuit determines the LC characteristics of the varactor tuning circuit which, in turn, determines the operating frequency of the VCO. One of the voltage control inputs is passed through an operational amplifier buffering stage before being transmitted to its respective terminal in the varactor tuning circuit. The LC-VCO utilizes a PMOS transistor core to provide good substrate isolation and low flicker (1/f) noise.

Abstract: A temperature-adaptive capacitor array used in a TCXO so that the TCXO effectively conducts temperature-compensating in the resonant frequency without the non-monotonicity while a smaller silicon area is used in producing the capacitor array. A number of capacitor arrays allocated in two capacitor banks. Each of the capacitor arrays comprises two or more unit cells, and in turn each unit cell consists of a unit capacitor and a switching element, respectively. All of unit capacitors included in the capacitor arrays are connected each other through a decoder assembly to provide a crystal oscillator with a load capacitance. The unit capacitors belonging to one of the capacitor arrays have the same capacitance with each other. Two unit capacitors belonging to different capacitor arrays, however, have different capacitances from each other.

Abstract: A PLL circuit includes: a phase comparator for comparing the phase of an input signal with the phase of a reference input signal to output a signal according to the phase difference therebetween; a low pass filter for outputting a low frequency control voltage on the basis of the output of the phase comparator; a voltage control oscillator for controlling an oscillating frequency on the basis of the control voltage; and a characteristic control part for controlling the characteristic of oscillating frequency to control voltage of the voltage control oscillator on the basis of n+1 ranges of first through n+1-th ranges obtained by dividing a variable range of the control voltage by first through n-th (n≧2) thresholds which are different from each other. Thus, it is possible to widen the operating frequency range, and it is possible to inhibit the frequency variation due to noises.