Abstract: A semiconductor package may include a substrate having an upper surface on which a plurality of first pads are disposed and a lower surface on which a plurality of second pads are disposed. The semiconductor package may further include a semiconductor chip disposed on the upper surface of the substrate on which connection electrodes connected to a first set of the plurality of first pads are disposed. The semiconductor package may include an interposer having an upper surface on which a plurality of first connection pads, connected to a second set of the plurality of first pads, and a plurality of second connection pads are disposed. The semiconductor package may further include a plurality of connection terminals disposed on a set of the plurality of second connection pads of the interposer, and a molding material disposed on the upper surface of the substrate.

Abstract: A semiconductor device including an active region protruding from an upper surface of a substrate and extending in a first horizontal direction, at least two gate electrodes extending in a second horizontal direction and crossing the active region, the second horizontal direction crossing the first horizontal direction, a source/drain region in the active region between the gate electrodes may be provided. The source/drain region includes a recess region, an outer doped layer on an inner wall of the recess region, an intermediate doped layer on the outer doped layer, and an inner doped layer on the intermediate doped layer and filling the recess region. One of the outer doped layer or the intermediate doped layer includes antimony, and the inner doped layer includes phosphorous.

Abstract: A first wafer, a method of fabricating thereof and a wafer stack are disclosed. The first wafer includes a first substrate, a first dielectric layer on the first substrate, first metal layers embedded in the first dielectric layer, first switching holes extending partially through the first dielectric layer and exposing the first metal layers, a first interconnection layer filling up the first switching holes and electrically connected to the first metal layers, a first insulating layer residing on surfaces of both the first dielectric layer and the first interconnection layer, first contact holes extending through the first insulating layer and exposing the first interconnection layer, and a second interconnection layer filling up the first contact holes and electrically connected to the first interconnection layer. Filling the first contact holes and the first switching holes with different interconnection layers reduces the difficulty in fabricating interconnection structures for the first metal layers.

Abstract: A method for manufacturing a display device is provided. A process of forming an inspection pattern, in which a protective film unit is partially removed in a thickness direction, in a pad area portion of the protective film unit, which corresponds to a pad area of a display unit, may be performed, and then, a process of delaminating the pad area portion of the protective film unit may be performed. A process of checking whether the inspection pattern exists may be performed to check whether the delamination has succeeded, and, at the same time, a process of measuring distances from an alignment mark to each of a long side and a short side of the display unit may be performed.

Abstract: Solid state transducer devices having integrated electrostatic discharge protection and associated systems and methods are disclosed herein. In one embodiment, a solid state transducer device includes a solid state emitter, and an electrostatic discharge device carried by the solid state emitter. In some embodiments, the electrostatic discharge device and the solid state emitter share a common first contact and a common second contact. In further embodiments, the solid state lighting device and the electrostatic discharge device share a common epitaxial substrate. In still further embodiments, the electrostatic discharge device is positioned between the solid state lighting device and a support substrate.

Abstract: A substrate structure includes a substrate, an encapsulating layer and a redistribution structure. The substrate has a first surface. The encapsulating layer surrounds the substrate and has a first surface. The redistribution structure is disposed on the first surface of the substrate and the first surface of the encapsulating layer. A gap exists in elevation between the first surface of the substrate and the first surface of the encapsulating layer.

Abstract: An interlayer film is deposited on a device layer on a substrate. A contact layer is deposited on the interlayer film. The interlayer film has a broken bandgap alignment to the device layer to reduce a contact resistance of the contact layer to the device layer.

Abstract: An imaging device that generates a pulse signal by utilizing photoelectric conversion operation is provided. A data potential generated by the photoelectric conversion operation is input to a pulse generation circuit to output a pulse signal having a spike waveform. In addition, a structure in which product-sum operation of pulse signals is performed is provided, and digital data is generated from a new pulse signal. The digital data is taken into a neural network or the like, whereby processing such as image recognition can be performed. Processing up to taking an enormous amount of image data into a neural network or the like can be performed in the imaging device; thus, processing can be efficiently performed.

Abstract: The present disclosure describes a method for forming ultra-thin fins with a tapered bottom profile for improved structural rigidity and gate control characteristics. The method includes forming a fin structure that includes an epitaxial layer portion and a doped region portion surrounded by an isolation region so that a top section of the epitaxial layer portion is above the isolation region. The method also includes depositing a silicon-based layer on the top portion of the epitaxial layer above the isolation region and annealing the silicon-based layer to reflow the silicon-based layer. The method further includes etching the silicon-based layer and the fin structure above the isolation region to form a first bottom tapered profile in the fin structure above the isolation region and annealing the fin structure to form a second bottom tapered profile below the first bottom tapered profile and above the isolation region.

Abstract: A method of forming a semiconductor device that includes forming an inner dielectric spacer and outer dielectric spacer combination structure on a sacrificial gate structure that is present on a fin structure, wherein the inner dielectric spacer and outer dielectric spacer combination structure separates source and drain regions from the sacrificial gate structure. The method further includes removing the inner sidewall dielectric spacer; and forming a channel epitaxial wrap around layer on the portion of the fin structure that is exposed by removing the inner sidewall dielectric spacer. The method further includes removing the sacrificial gate structure to provide a gate opening to a channel portion of the fin structure, wherein the gate opening exposes the channel epitaxial wrap around layer; and forming a functional gate structure within the gate opening.

Abstract: An integrated circuit package assembly includes a first integrated circuit package and a second integrated circuit package. The first integrated circuit package includes a first integrated circuit die mounted on a first substrate. The second integrated circuit package includes a second integrated circuit die mounted on a second substrate. The second integrated circuit package is disposed under the first integrated circuit package. Solder bumps are disposed between the first integrated circuit package and the second integrated circuit package and provide electrical signal connections between the first integrated circuit die and the second integrated circuit die. A buffer layer is disposed between the first substrate and the second integrated circuit die to facilitate thermal conduction between the first integrated circuit package and the second integrated circuit package.

Abstract: A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.

Abstract: A silicon-on-insulator (SOI) substrate includes a semiconductor substrate and a multi-layered polycrystalline silicon structure. The multi-layered polycrystalline silicon structure is disposed over the semiconductor substrate. The multi-layered polycrystalline silicon structure includes a plurality of doped polycrystalline silicon layers stacked over one another, and an oxide layer between each adjacent pair of doped polycrystalline silicon layers. A number of the doped polycrystalline silicon layer is ranging from 2 to 6.

Abstract: A semiconductor device includes lower gate electrodes placed on a substrate and spaced apart from one another; upper gate electrodes placed over the lower gate electrodes and spaced apart from one another; an R-type pad extending from one end of at least one electrode among the lower gate electrodes or the upper gate electrodes and having a greater thickness than the lower gate electrode or upper gate electrode connected to the R-type pad; and a P-type pad extending from one end of at least one electrode to which the R-type pad is not connected among the lower gate electrodes or the upper gate electrodes and having a different thickness than the R-type pad, wherein the P-type pad includes a first pad connected to an uppermost lower gate electrode among the lower gate electrodes.

Abstract: An integrated circuit includes a first and second set of gate structures. A center of each of the first set of gate structures is separated from a center of an adjacent gate of the first set of gate structures in a first direction by a first pitch. A center of each of the second set of gate structures is separated from a center of an adjacent gate of the second set of gate structures in the first direction by the first pitch. The first and second set of gate structures extend in a second direction. A gate of the first set of gate structures is aligned in the second direction with a corresponding gate of the second set of gate structures. The gate of the first set of gate structures is separated from the corresponding gate of second set of gate structures in the second direction by a first distance.

Abstract: A memory device is provided, which includes a substrate, a first memory cell, and a second memory cell. The first memory cell is arranged over the substrate and the second memory cell is arranged adjacent to the first memory cell. The first and second memory cells include a shared doped region arranged between the first and second memory cells.

Abstract: The instant disclosure discloses a method comprises receiving a substrate having a first region and a second region defined thereon and an insulating structure formed there-between; forming, extending across the first region and the second region, a gate stack including a dielectric layer and a gate poly layer formed thereon; forming a first well mask covering the second region while defining a first opening that projectively overlaps the first region to partially exposes the gate poly layer; performing a first doping process, through the first opening and the gate stack, to form a first well in the substrate beneath the first opening; and performing a second doping process through the first opening to form a first gate conductor in the gate poly layer.

Abstract: An integrated device package is disclosed. The package can include a carrier and an integrated device die having a front side and a back side. A mounting structure can serve to mount the back side of the integrated device die to the carrier. The mounting structure can comprise a first layer over the carrier and a second element between the back side of the integrated device die and the first layer. The first layer can comprise a first insulating material that adheres to the carrier, and the second element can comprise a second insulating material.

Abstract: A method to perform hybrid bonding of two semiconductor wafers without using a dedicated tool for thermo-compression is disclosed. According to the herein disclosed technique, the semiconductor wafers to be bonded together may be placed in an oven simply staying one upon the other without applying any additional compression between them besides their own weight. This outstanding result has been attained using of a particular type of thermosetting materials, namely siloxane polymers of the type that shrink when cured. Among these siloxane polymers, the siloxane polymers of the type SC-480, siloxane polymers of the series SC-200, SC-300, SC-400, SC-500, SC-700, SC-800 and mixtures thereof are particularly suitable.

Abstract: Resonant optical cavity light emitting devices are disclosed, where the device includes an opaque substrate, a first reflective layer, a first spacer region, a light emitting region, a second spacer region, and a second reflective layer. The light emitting region is configured to emit a target emission deep ultraviolet wavelength and is positioned at a separation distance from the reflector. The second reflective layer may have a metal composition comprising elemental aluminum and a thickness less than 15 nm. The device has an optical cavity comprising the first spacer region, the second spacer region and the light emitting region, where the optical cavity has a total thickness less than or equal to K·?/n. K is a constant ranging from 0.25 to 10, ? is the target wavelength, and n is an effective refractive index of the optical cavity at the target wavelength.