Abstract: A method includes providing a structure having a substrate and a fin. The fin has first and second layers of first and second different semiconductor materials. The first layers and the second layers are alternately stacked over the substrate. The structure further has a sacrificial gate stack engaging a channel region of the fin and gate spacers on sidewalls of the sacrificial gate stack. The method further includes etching a source/drain (S/D) region of the fin, resulting in an S/D trench; partially recessing the second layers exposed in the S/D trench, resulting in a gap between two adjacent layers of the first layers; and depositing a dielectric layer over surfaces of the gate spacers, the first layers, and the second layers. The dielectric layer partially fills the gap, leaving a void sandwiched between the dielectric layer on the two adjacent layers of the first layers.

Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.

Abstract: A semiconductor structure includes a semiconductor substrate including a first region and a second region; a first device disposed in the first region and a second device disposed in the second region, wherein a voltage level of the first device is greater than a voltage level of the second device; a first isolation disposed in the first region, wherein the first isolation includes a first depth; and a second isolation disposed in the second region, wherein the second isolation includes a second depth, and the first depth is greater than the second depth.

Abstract: A method may include forming a mask layer on top of a first dielectric layer formed on a first source/drain and a second source/drain, and creating an opening in the mask layer and the first dielectric layer that exposes portions of the first source/drain and the second source/drain. The method may include filling the opening with a metal layer that covers the exposed portions of the first source/drain and the second source/drain, and forming a gap in the metal layer to create a first metal contact and a second metal contact. The first metal contact may electrically couple to the first source/drain and the second metal contact may electrically couple to the second source/drain. The gap may separate the first metal contact from the second metal contact by less than nineteen nanometers.

Abstract: A first semiconductor substrate contains a first semiconductor material, such as silicon. A second semiconductor substrate containing a second semiconductor material, such as gallium nitride or aluminum gallium nitride, is formed on the first semiconductor substrate. The first semiconductor substrate and second semiconductor substrate are singulated to provide a semiconductor die including a portion of the second semiconductor material supported by a portion of the first semiconductor material. The semiconductor die is disposed over a die attach area of an interconnect structure. The interconnect structure has a conductive layer and optional active region. An underfill material is deposited between the semiconductor die and die attach area of the interconnect structure. The first semiconductor material is removed from the semiconductor die and the interconnect structure is singulated to separate the semiconductor die. The first semiconductor material can be removed post interconnect structure singulation.

Abstract: According to one embodiment, a semiconductor device includes first, second and third conductive parts, a first semiconductor region, and a first insulating part. A direction from the first conductive part toward the second conductive part is along a first direction. The first semiconductor region includes first, second, and third partial regions. A second direction from the first partial region toward the second partial region crosses the first direction. The third partial region is between the first partial region and the second conductive part in the first direction. The third partial region includes an opposing surface facing the second conductive part. A direction from the opposing surface toward the third conductive part is along the second direction. The first insulating part includes a first insulating region. At least a portion of the first insulating region is between the opposing surface and the third conductive part.

Abstract: The present disclosure is directed to a method of fabrication a semiconductor structure. The method includes providing a substrate and forming a bottom electrode over the substrate, wherein a terminal end of the bottom electrode has a tapered sidewall. The method also includes depositing an insulating layer over the bottom electrode and forming a top electrode over the insulating layer, wherein a terminal end of the top electrode has a vertical sidewall.

Abstract: A device includes a base substrate with a sensor component arranged thereon; a spacer layer on the base substrate, wherein the spacer layer is structured in order to predefine a cavity region, in which the sensor component is arranged in an exposed fashion on the base substrate, and a DAF tape element (DAF=Die-Attach-Film) on a stack element, wherein the DAF tape element mechanically fixedly connects the stack element to the spacer layer arranged on the base substrate and to obtain the cavity region.

Abstract: A display apparatus includes a substrate, a display unit disposed on the substrate, an insulating layer disposed on the substrate, a power supply wire disposed on the insulating layer outside the display unit, and a cladding layer. The display unit includes a pixel circuit and a display element electrically connected to the pixel circuit. The insulating layer extends from the display unit to an edge of the substrate. The power supply wire is electrically connected to the display element and includes an alignment pattern that exposes at least a portion of the insulating layer. The cladding layer covers an inner surface of the alignment pattern and contacts the at least a portion of the insulating layer.

Abstract: Provided is a semiconductor isolation structure including: a substrate having a first trench in a first region of the substrate and a second trench in a second region of the substrate; a filling layer is located in the first trench and the second trench; a liner layer on the sidewalls and bottom of the first trench and the second trench; a fixed negative charge layer is located between the filling layer and the liner layer in the first trench and the second trench; and a fixed positive charge layer located between the fixed negative charge layer and the liner layer in the first trench. The liner layer, the fixed positive charge layer, the fixed negative charge layer and the filling layer in the first trench form a first isolation structure. The liner layer, the fixed negative charge layer and the filling layer in the second trench form a second isolation structure.

Abstract: A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated.

Abstract: Electrical device including a substrate having a surface and a radiofrequency field effect transistor (RF-FET) on the substrate surface. RF-FET includes a CNT layer on the substrate surface, the CNT layer including electrically conductive aligned carbon nanotubes, and pin-down anchor layers on the CNT layer. A first portion of the CNT layer, located in-between the pin-down anchor layers, is not covered by the pin-down anchor layers and is a channel region of the radiofrequency field effect transistor and second portions of the CNT layer are covered by the pin-down anchor layers. For cross-sections in a direction perpendicular to a common alignment direction of the aligned CNTs in the first portion of the CNT layer: the aligned CNTs have an average linear density in a range from 20 to 120 nanotubes per micron along the cross-section, and at least 40 percent of the aligned CNTs are discrete from any CNTs of the CNT layer.

Abstract: Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.

Abstract: A method of forming a semiconductor device includes following steps. A semiconductor strip is formed extending above a semiconductor substrate. A shallow trench isolation (STI) region is formed over the semiconductor substrate. The semiconductor strip has a fin structure higher than a top surface of the STI region. The fin structure includes a channel portion and a source/drain (S/D) portion adjacent to the channel portion. A dummy gate stack is formed over the channel portion. The S/D portion is exposed by the dummy gate stack. A doping process is performed to a top of the S/D portion using first dopants. An epitaxy layer is formed around the top of the S/D portion. The epitaxy layer has second dopants. A conductivity type of the second dopants is different from a conductivity type of the first dopants. The dummy gate stack is replaced with a replacement gate stack.

Abstract: A transparent organic light emitting display apparatus and a method of manufacturing the same are discussed. The transparent organic light emitting display apparatus can comprise an emission area, a transmission area disposed adjacent to the emission area and configured to pass external light therethrough, and an undercut area formed in the transmission area, wherein the undercut area is filled by an encapsulation layer.

Abstract: Manufacturing method of semiconductor package includes following steps. Bottom package is provided. The bottom package includes a die and a redistribution structure electrically connected to die. A first top package and a second top package are disposed on a surface of the redistribution structure further away from the die. An underfill is formed into the space between the first and second top packages and between the first and second top packages and the bottom package. The underfill covers at least a side surface of the first top package and a side surface of the second top package. A hole is opened in the underfill within an area overlapping with the die between the side surface of the first top package and the side surface of the second top package. A thermally conductive block is formed in the hole by filling the hole with a thermally conductive material.

Abstract: In order to improve the reliability of a semiconductor device, in a memory cell of a split-gate type MONOS memory formed on a fin, a drain region is formed in an epitaxial layer on the fin, and a source region is formed in the fin, and a silicide layer is formed on an upper surface of the fin in which the source region is formed.

Abstract: Printable and stretchable thin-film devices and fabrication techniques are provided for forming fully-printed, intrinsically stretchable thin-film transistors and integrated logic circuits using stretchable elastomer substrates such as polydimethylsiloxane (PDMS), semiconducting carbon nanotube network as channel, unsorted carbon nanotube network as source/drain/gate electrodes, and BaTiO3/PDMS composite as gate dielectric. Printable stretchable dielectric layer ink may be formed by mixing barium titanate nanoparticle (BaTiO3) with PDMS using 4-methyl-2-pentanone as solvent.

Abstract: Embodiments of the invention are directed to a method of performing fabrication operations to form a transistor, wherein the fabrication operations include forming a source or drain (S/D) region having an S/D formation assistance region at least partially within a portion of a substrate. An S/D isolation region is formed around sidewalls and a bottom surface of the S/D formation assistance region and configured to electrically isolate the S/D formation assistance region from the substrate.

Abstract: A semiconductor device includes: a first fin and a second fin extending from a substrate and an epitaxial source/drain region. The epitaxial source/drain region includes a first portion grown on the first fin and a second portion grown on the second fin, and the first portion and the second portion are joined at a merging boundary. The epitaxial source/drain region further includes a first subregion extending from a location level with a highest point of the epitaxial source/drain region to a location level with a highest point of the merging boundary, a second subregion extending from the location level with the highest point of the merging boundary to a location level with a lowest point of the merging boundary, and a third subregion extending from the location level with the lowest point of the merging boundary to a location level with a top surface of an STI region.