Patents Examined by Sonya McCall-Shepard
  • Semiconductor epitaxial wafer and method of producing semiconductor epitaxial wafer, and method of producing solid-state imaging device
    Patent number: 11107687
    Abstract: Provided is a semiconductor epitaxial wafer in which the concentration of hydrogen in a modifying layer can be maintained at a high level and the crystallinity of an epitaxial layer is excellent. A semiconductor epitaxial wafer has a semiconductor wafer, a modifying layer formed in a surface portion of the semiconductor wafer, which modifying layer has hydrogen contained as a solid solution in the semiconductor wafer, and an epitaxial layer formed on the modifying layer. The concentration profile of hydrogen in the modifying layer in the thickness direction from a surface of the epitaxial layer is a double peak concentration profile including a first peak shallower in the depth direction and a second peak deeper in the depth direction.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: August 31, 2021
    Assignee: SUMCO CORPORATION
    Inventor: Ryosuke Okuyama
  • Structure and formation method of semiconductor device structure with gate stack
    Patent number: 11101344
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Lin, Chih-Lin Wang, Kang-Min Kuo
  • Methods of forming an array of elevationally-extending strings of memory cells, methods of forming polysilicon, elevationally-extending strings of memory cells individually comprising a programmable charge storage transistor, and electronic components comprising polysilicon
    Patent number: 11094705
    Abstract: A method of forming polysilicon comprises forming a first polysilicon-comprising material over a substrate, with the first polysilicon-comprising material comprising at least one of elemental carbon and elemental nitrogen at a total of 0.1 to 20 atomic percent. A second polysilicon-comprising material is formed over the first polysilicon-comprising material. The second polysilicon-comprising material comprises less, if any, total elemental carbon and elemental nitrogen than the first polysilicon-comprising material. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: August 17, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Dimitrios Pavlopoulos, Kunal Shrotri, Anish A. Khandekar
  • Semiconductor structure having active regions with different dopant concentrations
    Patent number: 11094692
    Abstract: A semiconductor structure includes a first semiconductor substrate, a second semiconductor substrate, a depletion layer, an isolation structure, a first gate structure, and a second gate structure. The first and second semiconductor substrates respectively have a first active region and a second active region overlapping the first active region. The depletion layer is disposed between the first active region and the second active region. The isolation structure surrounds the first and second active regions. The first gate structure is disposed in the second active region. The second gate structure is disposed in the second active region. The second active region has a portion between the first gate structure and the second gate structure.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: August 17, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ching-Chia Huang, Tseng-Fu Lu
  • Doped and undoped vanadium oxides for low-k spacer applications
    Patent number: 11094533
    Abstract: A microelectronic device on a semiconductor substrate comprises: a gate electrode; and a spacer adjacent to the gate electrode, the spacer comprising: a the low-k dielectric film comprising one or more species of vanadium oxide, which is optionally doped, and an optional silicon nitride or oxide film. Methods comprise depositing a low-k dielectric film optionally sandwiched by a silicon nitride or oxide film to form a spacer adjacent to a gate electrode of a microelectronic device on a semiconductor substrate, wherein the low-k dielectric film comprises a vanadium-containing film.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: August 17, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Eswaranand Venkatasubramanian, Srinivas Gandikota, Kelvin Chan, Atashi Basu, Abhijit Basu Mallick
  • Packaged semiconductor device with electroplated pillars
    Patent number: 11094656
    Abstract: In a described example, a device includes an overcoat layer covering an interconnect; an opening in the overcoat layer exposing a portion of a surface of the interconnect; a stud on the exposed portion of the surface of the interconnect in the opening; a surface of the stud approximately coplanar with a surface of the overcoat layer; and a conductive pillar covering the stud and covering a portion of the overcoat layer surrounding the stud, the conductive pillar having a planar and un-dished surface facing away from the stud and the overcoat layer.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: August 17, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Arvin Cedric Quiambao Mallari, Maricel Fabia Escano, Armando Tresvalles Clarina, Jr., Jovenic Romero Esquejo
  • Wimpy device by selective laser annealing
    Patent number: 11088026
    Abstract: A device having co-integrated wimpy and nominal transistors includes first source/drain regions formed with a semiconductor alloy imparting strain into a first channel region. The device also has wimpy transistors including second source/drain regions formed with the semiconductor alloy that has been decomposed to include a larger amount of an electrically active atomic element than contained in the semiconductor alloy of the first source/drain region.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: August 10, 2021
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Kangguo Cheng, Nicolas J. Loubet, Xin Miao, Alexander Reznicek
  • High voltage (HV) metal oxide semiconductor field effect transistor (MOSFET) in semiconductor on insulator (SOI) technology
    Patent number: 11081582
    Abstract: A method of constructing an integrated circuit (IC) includes fabricating a metal oxide semiconductor field effect transistor (MOSFET) on a first surface of an insulator layer of the integrated circuit. The insulator layer is supported by a sacrificial substrate. The MOSFET includes an extended drain region. The method deposits a front-side dielectric layer on the MOSFET, bonds a handle substrate to the front-side dielectric layer, and then removes the sacrificial substrate. The method also fabricates multiple back gates on a second surface of the insulator layer. The second surface is opposite the first surface.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: August 3, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Qingqing Liang, Ravi Pramod Kumar Vedula, Sivakumar Kumarasamy, George Pete Imthurn, Sinan Goktepeli
  • High power module package structures
    Patent number: 11075137
    Abstract: A dual-side cooling package includes a first semiconductor die and a second semiconductor die disposed between a first direct bonded metal (DBM) substrate and a second DBM substrate. A metal surface of the first DBM substrate defines a first outer surface of a package and a metal surface of the second DBM substrate defines a second outer surface of the package. The first semiconductor die is thermally coupled to the first DBM substrate. A first conductive spacer thermally couples the first semiconductor die to the second DBM substrate. The second semiconductor die is thermally coupled to a second conductive spacer. Further, one of the second semiconductor die and the second conductive spacer is thermally coupled to the first DMB substrate and the other of the second semiconductor die and the second conductive spacer is thermally coupled to the second DBM substrate.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: July 27, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng Lin, Jerome Teysseyre
  • Integrated circuit including a low-noise amplifying circuit with asymmetrical source and drain regions and a logic circuit with symmetrical source and drain regions
    Patent number: 11069806
    Abstract: An integrated circuit includes a logic circuit and an amplifying circuit, in particular a low-noise amplifying circuit. The amplifying circuit includes at least one first transistor. The gate of the first transistor is coupled to a signal input terminal, the source region and the drain region of the first transistor are formed respectively in the well region of the first transistor on both sides of the gate, wherein the source region is coupled to a reference voltage terminal, and the sheet resistance of the source region is lower than that of the drain region. The logic circuit includes at least one second transistor. The sheet resistances of the source region and the drain region of the second transistor are equal.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: July 20, 2021
    Assignee: RichWave Technology Corp.
    Inventors: Chuan-Chen Chao, Shyh-Chyi Wong, Shu-Yuan Hsu
  • Contact structure
    Patent number: 11062908
    Abstract: A semiconductor device includes: a fin structure disposed on a substrate; a gate feature that traverses the fin structure to overlay a central portion of the fin structure; a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature; and a plurality of contact structures that are formed of tungsten, wherein a gate electrode of the gate feature and the pair of source/drain features are each directly coupled to a respective one of the plurality of contact structures.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hong-Ying Lin, Cheng-Yi Wu, Alan Tu, Chung-Liang Cheng, Li-Hsuan Chu, Ethan Hsiao, Hui-Lin Sung, Sz-Yuan Hung, Sheng-Yung Lo, C. W. Chiu, Chih-Wei Hsieh, Chin-Szu Lee
  • Integrated circuit and method for manufacturing same
    Patent number: 11062075
    Abstract: A method of manufacturing an integrated circuit includes generating a layout design of the integrated circuit, manufacturing the integrated circuit based on the layout design, and removing a portion of a gate structure of a set of gate structures thereby forming a first and a second gate structure. Generating the layout design includes placing a set of gate layout patterns and a cut feature layout pattern on the first layout level. The cut feature layout pattern extends in a first direction, overlaps the set of gate layout patterns and identifies a location of the portion of the gate structure of the set of gate structures. The set of gate layout patterns correspond to fabricating a set of gate structures. The set of gate layout patterns extending in a second direction and overlapping a set of gridlines that extend in the second direction.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jung Chang, Chin-Chang Hsu, Hsien-Hsin Sean Lee, Wen-Ju Yang
  • Semiconductor device and fingerprint identification device
    Patent number: 11049771
    Abstract: A method for forming a semiconductor device is provided. The method includes providing a substrate, placing a first stencil having a first openwork pattern on the substrate, applying a first material onto the substrate through the first stencil, and removing the first stencil from the substrate. The first material includes a transparent material. The method also includes placing a second stencil having a second openwork pattern on the substrate, applying a second material onto the substrate through the second stencil, and removing the second stencil from the substrate. The second material includes a light-shielding material, and the second openwork pattern is different from the first openwork pattern.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: June 29, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Han-Liang Tseng, Hsin-Hui Lee, Hsueh-Jung Lin
  • Method and structure for forming silicon germanium finFET
    Patent number: 11049940
    Abstract: A method of a forming a plurality of semiconductor fin structures that includes forming a sacrificial gate structure on a hardmask overlying a channel region portion of the plurality of sacrificial fins of a first semiconductor material and forming source and drain regions on opposing sides of the channel region. The sacrificial gate structure and the sacrificial fin structure are removed. A second semiconductor material is formed in an opening provided by removing the sacrificial gate structure and the sacrificial fin structure. The second semiconductor material is etched selective to the hardmask to provide a plurality of second semiconductor material fin structures. A function gate structure is formed on the channel region.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: June 29, 2021
    Assignee: International Business Machines Corporation
    Inventors: Peng Xu, Kangguo Cheng, Juntao Li, Heng Wu
  • Method of manufacturing semiconductor apparatus including measuring a film thickness of an SOG film
    Patent number: 11037840
    Abstract: A plurality of semiconductor devices (5) are formed on a semiconductor wafer (1). A film thickness measurement wiring pattern (3,4) is formed on a dicing line (6,7) defining the plurality of semiconductor devices (5). An SOG film (10) is formed on the semiconductor devices (5) and the film thickness measurement wiring pattern (3,4). A film thickness of the SOG film (10) at a central part of the film thickness measurement wiring pattern (3,4) is measured. The film thickness measurement wiring pattern (3,4) is a rectangular pattern having long sides parallel to the dicing line (3,4).
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: June 15, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yuji Kawasaki
  • Stacked semiconductor structure and method
    Patent number: 11037909
    Abstract: A device comprises a first chip comprising a first connection pad embedded in a first dielectric layer and a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad and a second chip comprising a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ying Chen, Meng-Hsun Wan, Dun-Nian Yaung
  • Cell boundary structure for embedded memory
    Patent number: 11031409
    Abstract: Various embodiments of the present application are directed to an embedded memory boundary structure with a boundary sidewall spacer, and associated forming methods. In some embodiments, an isolation structure is disposed in a semiconductor substrate to separate a memory region from a logic region. A memory cell structure is disposed on the memory region and a cell boundary structure is formed on the isolation structure including a boundary sidewall spacer. A protecting dielectric layer is disposed on a top surface of the boundary sidewall spacer. The boundary sidewall spacer and the protecting dielectric layer provide a smooth boundary sidewall that is not subject to damage during formation of the logic device structure and, hence, is not subject to trapping high ? etch residue during formation of the logic device structure with HKMG technology.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Han Lin, Chih-Ren Hsieh, Wei Cheng Wu, Chih-Pin Huang
  • Nano-photonics reflector for LED emitters
    Patent number: 11024767
    Abstract: A system, method and device for use as a reflector for a light emitting diode (LED) are disclosed. The system, method and device include a first layer designed to reflect transverse-electric (TE) radiation emitted by the LED, a second layer designed to block transverse-magnetic (TM) radiation emitted from the LED, and a plurality of ITO layers designed to operate as a transparent conducting oxide layer. The first layer may be a one-dimension (1D) distributed Bragg reflective (DBR) layer. The second layer may be a two-dimension (2D) photonic crystal (PhC), a three-dimension (3D) PhC, and/or a hyperbolic metamaterial (HMM). The 2D PhC may include horizontal cylinder bars, vertical cylinder bars, or both. The system, method and device may include a bottom metal reflector that may be Ag free and may act as a bonding layer.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: June 1, 2021
    Assignee: Lumileds LLC
    Inventors: Toni Lopez, Venkata Ananth Tamma
  • Protective passivation layer for magnetic tunnel junctions
    Patent number: 11024798
    Abstract: A magnetic device for magnetic random access memory (MRAM), spin torque MRAM, or spin torque oscillator technology is disclosed wherein a magnetic tunnel junction (MTJ) with a sidewall is formed between a bottom electrode and a top electrode. A passivation layer that is a single layer or multilayer comprising one of B, C, or Ge, or an alloy thereof wherein the B, C, and Ge content, respectively, is at least 10 atomic % is formed on the MTJ sidewall to protect the MTJ from reactive species during subsequent processing including deposition of a dielectric layer that electrically isolates the MTJ from adjacent MTJs, and during annealing steps around 400° C. in CMOS fabrication. The single layer is about 3 to 10 Angstroms thick and may be an oxide or nitride of B, C, or Ge. The passivation layer is preferably amorphous to prevent diffusion of reactive oxygen or nitrogen species.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jodi Mari Iwata, Guenole Jan, Ru-Ying Tong
  • Methods for fabricating artificial neural networks (ANN) based on doped semiconductor resistive random access memory (RRAM) elements
    Patent number: 11024803
    Abstract: A method of forming a resistive random access memory (RRAM) element, the method includes forming a Silicon layer on an oxide layer, depositing a thin film dopant layer on the Silicon layer, and controlling a concentration of the dopant in the thin film dopant layer.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: June 1, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Matthew Warren Copel, James Bowler Hannon, Satoshi Oida