Patents Examined by Stanetta D Isaac
  • Semiconductor memory device
    Patent number: 10396091
    Abstract: According to an embodiment, a semiconductor memory device comprises control gate electrodes, a first semiconductor layer, a gate insulating layer, a first contact, a second semiconductor layer, a second contact, and a first conductive layer. The control gate electrodes are stacked above a substrate. The first semiconductor layer faces the control gate electrodes. The gate insulating layer is provided between the control gate electrode and the first semiconductor layer. The first contact is connected to an upper end of the first semiconductor layer. The second contact is connected to a lower end of the first semiconductor layer via the second semiconductor layer. The first conductive layer is provided above the second contact. Moreover, an end of the first conductive layer closest to the first contact is closer to the first contact than an end of the second contact closest to the first contact.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: August 27, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kei Sakamoto
  • Tungsten feature fill with nucleation inhibition
    Patent number: 10381266
    Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to ammonia vapor in a non-plasma process. Process parameters including exposure time, substrate temperature, and chamber pressure can be used to tune the inhibition profile. Also provided are methods of filling multiple adjacent lines with reduced or no line bending. The methods involve selectively inhibiting the tungsten nucleation to reduce sidewall growth during feature fill.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: August 13, 2019
    Assignee: Novellus Systems, Inc.
    Inventors: Tsung-Han Yang, Anand Chandrashekar, Jasmine Lin
  • Controlling oxygen concentration levels during processing of highly-reflective contacts
    Patent number: 10374122
    Abstract: Techniques for controlling oxygen concentration levels during annealing of highly-reflective contacts for LED devices together with lamps, LED device and method embodiments thereto are disclosed.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: August 6, 2019
    Assignee: SORAA, INC.
    Inventors: Christophe Hurni, Remi Delille
  • Method of separating electronic devices having a back layer and apparatus
    Patent number: 10366923
    Abstract: A method of singulating a wafer includes providing a wafer having a plurality of die formed as part of the wafer and separated from each other by spaces. The wafer has first and second opposing major surfaces and a layer of material disposed along the second major surface. The method includes placing the wafer onto a carrier substrate and etching through the spaces to form singulation lines, wherein etching comprises stopping atop the layer of material. The method includes providing an apparatus comprising a compression structure, a support structure, and a transducer system configured to apply high frequency mechanical vibrations to the layer of material. The method includes placing the wafer and the carrier substrate onto the support structure, and, in one embodiment, applying pressure and mechanical vibrations to the wafer to separate the layer of material in the singulation lines.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: July 30, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Gordon M. Grivna
  • Semiconductor devices and methods for manufacturing the same
    Patent number: 10366997
    Abstract: A semiconductor device includes a substrate including first and second active patterns thereon, a first gate electrode intersecting the first and second active patterns, first and second source/drain regions on the first and second active patterns, respectively, at one side of the first gate electrode, and an active contact on the first source/drain region so as to be electrically connected to the first source/drain region. The active contact includes a first sub-contact and a second sub-contact. The second sub-contact includes a vertical extension vertically extending toward the substrate. A bottom surface of the vertical extension is lower than a bottom surface of the first sub-contact.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: July 30, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Changseop Yoon
  • Semiconductor devices and methods of fabricating the same
    Patent number: 10361194
    Abstract: Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: July 23, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon-Kyu Park, Jae-Yeol Song, Hoon-Joo Na, Yoon-Tae Hwang, Ki-Joong Yoon, Sang-Jin Hyun
  • Optically enhanced solid-state light converters
    Patent number: 10353280
    Abstract: A light converter (200) comprises: a solid-state light conversion material (201) that generates emission light from excitation light incident on its surface; a filler layer (230, 240) on the surface of the solid-state light conversion material (201); and an optical coating (220, 250) on the filler layer. The optical coating (220, 250) may be a thin film, such as an anti-reflective coating (220) and/or a high-reflective coating (250). A metallic coating (260) may additionally be provided. The light converter (200) may be used for an optical device, such as a phosphor wheel or automotive headlight.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: July 16, 2019
    Assignee: MATERION CORPORATION
    Inventors: Yuyong Huang, Simon Cao
  • Trench isolation structures and methods for forming the same
    Patent number: 10347524
    Abstract: A trench isolation structure is provided. The trench isolation structure includes a substrate. A polygonal trench is disposed in the substrate. An insulating material is disposed in the polygonal trench, and a polygon top-side contact structure is disposed in the polygonal trench and surrounded by the insulating material. The polygon top-side contact structure has the same shape as the polygonal trench from a top view. A method for forming the trench isolation structure is also provided.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: July 9, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Hsiung-Shih Chang, Jui-Chun Chang, Li-Che Chen
  • Method of fabricating light emitting diode module
    Patent number: 10332865
    Abstract: A method of fabricating a LED module includes preparing a circuit board, such that the circuit board includes a reflective laminate around a chip mounting region and an electrode pad in the chip mounting region, preparing a mask, such that the mask includes a protruding portion with a discharge hole, and the protruding portion is inserted into a space surrounded by the reflective laminate, dispensing solder paste onto the electrode pad using the mask, and bonding an electrode of a LED chip to the electrode pad of the circuit board using the solder paste.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun Kim, Jae Jun Bang, Chang Ho Shin, Dong Soo Lee, Seog Ho Lim, Myoung Sun Ha
  • Diffused tip extension transistor
    Patent number: 10304956
    Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Pratik A. Patel, Mark Y. Liu, Jami A. Wiedemer, Paul A. Packan
  • Semiconductor device and manufacturing method thereof
    Patent number: 10304743
    Abstract: A semiconductor device according to this embodiment includes a semiconductor layer, a plurality of diffusion layers in the semiconductor layer, a gate insulating film, a gate electrode, first contacts, and second contacts. The gate insulating film is on the semiconductor layer between the plurality of diffusion layers. The gate electrode is on the gate insulating film. The first contacts include silicide layers of the same material which are on the gate electrode and the diffusion layers respectively, and first metal layers on the silicide layers. The second contacts are on the first contacts.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: May 28, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Naomi Fukumaki, Masaaki Hatano, Seiichi Omoto
  • Semiconductor devices and methods for forming the same
    Patent number: 10276563
    Abstract: A semiconductor device and a method for forming the same are provided. The method includes forming a patterned mask on a substrate, wherein the patterned mask includes a pad oxide layer and a silicon nitride layer over the pad oxide layer. The method also includes forming a trench in the substrate by performing a first etching process on the substrate through an opening of the patterned mask and forming a dielectric material layer in the trench, in the opening, and on the patterned mask. The method further includes performing a planarization process to remove the dielectric material layer outside of the trench, and performing a heat treatment process to form an oxidized portion at the interface of the pad oxide layer and the substrate and adjacent to the dielectric material layer.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: April 30, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Ying-Kai Chou, Li-Che Chen, Hsing-Chao Liu
  • Semiconductor device and method of manufacturing the same
    Patent number: 10269946
    Abstract: A semiconductor device including an IGBT element having features of a low on-state voltage and a low turn-off loss is provided. The semiconductor device is comprised of a trench gate type IGBT element. The IGBT element includes: a plurality of gate trench electrodes to which gate potential is given; and a plurality of emitter trench electrodes to which emitter potential is given. Between adjacent trench electrodes, a contact to an emitter electrode layer is formed. In this regard, there is formed, in the semiconductor substrate, a P type floating region which is in contact with bottom portions of at least some of the emitter trench electrodes via an interlayer insulation layer.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: April 23, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Hitoshi Matsuura
  • Semiconductor package and a method of manufacturing the same
    Patent number: 10269677
    Abstract: A method to manufacture a semiconductor package includes: preparing a metal substrate; attaching semiconductor dies to the metal substrate at an interval; attaching a bonding film to the semiconductor dies; applying a mold material on the semiconductor dies and the metal substrate, and curing the mold material to form a mold member; grinding the mold member and the metal substrate to a thickness; removing the bonding film; attaching a redistribution layer to the semiconductor dies; and cutting between the semiconductor dies.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: April 23, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Jae Sik Choi, Dong Seong Oh, Si Hyeon Go
  • Semiconductor device with deep diffusion region
    Patent number: 10263101
    Abstract: A method of processing a semiconductor device, comprising: providing a semiconductor body having dopants of a first conductivity type; forming at least one trench that extends into the semiconductor body along a vertical direction, the trench being laterally confined by two trench sidewalls and vertically confined by a trench bottom; applying a substance onto at least a section of a trench surface formed by one of the trench sidewalls and/or the trench bottom of the at least one trench, such that applying the substance includes preventing that the substance is applied to the other of the trench sidewalls; and diffusing of the applied substance from the section into the semiconductor body, thereby creating, in the semiconductor body, a semiconductor region having dopants of a second conductivity type and being arranged adjacent to the section.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: April 16, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thomas Wuebben, Peter Irsigler, Hans-Joachim Schulze
  • Semiconductor device and method for fabricating the same
    Patent number: 10256297
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate, forming a gate structure on the substrate, forming a hard mask on the substrate and the gate structure, patterning the hard mask to form trenches exposing part of the substrate, and forming raised epitaxial layers in the trenches. Preferably, the gate structure is extended along a first direction on the substrate and the raised epitaxial layers are elongated along a second direction adjacent to two sides of the gate structure.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: April 9, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wanxun He, Su Xing
  • Monolithic integration of antenna switch and diplexer
    Patent number: 10256863
    Abstract: An integrated radio frequency (RF) circuit structure may include a resistive substrate material and a switch. The switch may be arranged in a silicon on insulator (SOI) layer supported by the resistive substrate material. The integrated RF circuit structure may also include an isolation layer coupled to the SOI layer. The integrated RF circuit structure may further include a filter, composed of inductors and capacitors. The filter may be arranged on a surface of the integrated RF circuit structure, opposite the resistive substrate material. In addition, the switch may be arranged on a first surface of the isolation layer.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: April 9, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Shiqun Gu, Chengjie Zuo, Steve Fanelli, Thomas Gee, Young Kyu Song
  • Aspect ratio trapping in channel last process
    Patent number: 10249736
    Abstract: A method of forming the fin structure that includes forming a replacement gate structure on a channel region of the at least one replacement fin structure; and forming an encapsulating dielectric encapsulating the replacement fin structure leaving a portion of the replacement gate structure exposed. The exposed portion of the replacement gate structure is etched to provide an opening through the encapsulating dielectric to the replacement fin structure. The replacement fin structure is etched selectively to the dielectric to provide a fin opening having a geometry dictated by the encapsulating dielectric. Functional fin structures of a second semiconductor material is epitaxially grown on the growth surface of the substrate substantially filling the fin opening.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Chun-chen Yeh
  • Circuit design having aligned power staples
    Patent number: 10242946
    Abstract: A multi-layer integrated circuit structure includes (among other components) a first layer having gate conductors, a second layer having M0 conductors, a third layer having M1 conductors, and a fourth layer having M2 conductors. The M0 and M2 conductors are perpendicular to the gate conductors, and parallel to each other. The M1 conductors connect the M0 conductors to the M2 conductors. The gate conductors are positioned in the first layer in the same locations in the horizontal direction. The M1 conductors are positioned in the third layer in a different location in the horizontal direction that is different from the locations of the gate conductors, so that the M1 conductors do not overlap any of the gate conductors, solving a substantial routing challenge for the input and output contacts.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: March 26, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Irene Y. L. Lin, Lei Yuan, Mahbub Rashed
  • Method of manufacturing a semiconductor device
    Patent number: 10236399
    Abstract: Provided is a method of manufacturing a semiconductor device having a photodiode that has a shallow p-n junction and thus achieves high sensitivity to an ultraviolet ray, in which an oxide containing impurities at high concentration is deposited on the surface of the silicon substrate, and thereafter a diffusion region is formed to have a shallow junction by performing thermal diffusion of a rapid temperature change, with the use of a high-speed temperature rising and falling apparatus without using ion implantation into the silicon substrate.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: March 19, 2019
    Assignee: ABLIC INC.
    Inventor: Tatsuya Aso