Abstract: An LED display includes a wafer-level substrate, a first adhesive layer, a plurality of first light-emitting assemblies, and a first conductive structure. The wafer-level substrate includes a plurality of control circuits, each of which has a conductive contact. The first adhesive layer is disposed on the wafer-level substrate. Each first light-emitting assembly includes a plurality of first LED structures disposed on the first adhesive layer. The first conductive structure is electrically connected between the corresponding first LED structure and the control circuit. Thereby, each first light-emitting assembly including a plurality of first LED structures and a wafer-level substrate having a plurality of control circuits can be connected to each other through a first adhesive layer.

Abstract: A semiconductor device of the present invention includes a substrate having a drift layer, metal wiring formed on an upper surface of the substrate, and an electrode formed on a back surface of the substrate, wherein the lifetime of carriers in the drift layer satisfies the following expression 1: [Expression 1] ??1.5×10?5 exp(5.4×103tN?)??expression 1 ?: the lifetime of carriers in the drift layer tN?: the layer thickness of the drift layer.

Abstract: In one example, an electroplating system comprises a first bath reservoir, a second bath reservoir, a clamp, a first anode in the first bath reservoir, a second anode in the second bath reservoir, and a direct current power supply. The first bath reservoir contains a first electrolyte solution that includes an alkaline copper-complexed solution. The second bath reservoir contains a second electrolyte solution that includes an acidic copper plating solution. The direct current power supply generates a first direct current between the clamp and the first anode to electroplate a first copper layer on the cobalt layer of the wafer submerged in the first electrolyte solution. The direct current power supply then generates a second direct current between the clamp and the second anode to electroplate a second copper layer on the first copper layer of the wafer submerged in the second electrolyte solution.

Abstract: A display device includes a first substrate, a second substrate, a first conductive layer, a first insulating layer, a second conductive layer and a spacer. The second substrate is disposed opposite to the first substrate. The first conductive layer is disposed on the first substrate and includes the first conductive line and the first dummy pad thereon. The first dummy pad and the first conductive line are disposed adjacent to each other. The first insulating layer is disposed on the first conductive layer. The second conductive layer is disposed on the first insulating layer and include a conductive pad partially overlap the first dummy pad. The spacer is disposed between the first substrate and the second substrate and partially overlaps the first conductive line.

Abstract: A semiconductor device of the present invention includes a substrate having a drift layer, metal wiring formed on an upper surface of the substrate, and an electrode formed on a back surface of the substrate, wherein the lifetime of carriers in the drift layer satisfies the following expression 1: [Expression 1] ??1.5×10?5 exp(5.4×103tN?)??expression 1 ?: the lifetime of carriers in the drift layer tN?: the layer thickness of the drift layer.

Abstract: A method is provided for monitoring the laser annealing of a semiconductor wafer. After annealing, images of many regions of the wafer are captured. The surface brightness of these regions is measured by computer, and statistics of these surface brightness measurements are determined, such as their mean and their standard deviation. Using a correlation between the surface brightnesses and the electrical resistance of the annealed wafer, the surface brightness statistics can be used to determine whether the annealing process resulted in a wafer that meets end user specifications. The surface brightness statistics can also be used to monitor the annealing tool, both during manufacturing and periodically or following maintenance.

Abstract: A power semiconductor device including a first and second die, each including a plurality of conductive contact regions and a passivation region including a number of projecting dielectric regions and a number of windows. Adjacent windows are separated by a corresponding projecting dielectric region with each conductive contact region arranged within a corresponding window. A package of the surface mount type houses the first and second dice. The package includes a first bottom insulation multilayer and a second bottom insulation multilayer carrying, respectively, the first and second dice. A covering metal layer is arranged on top of the first and second dice and includes projecting metal regions extending into the windows to couple electrically with corresponding conductive contact regions. The covering metal layer moreover forms a number of cavities, which are interposed between the projecting metal regions so as to overlie corresponding projecting dielectric regions.

Abstract: A deposition system that mitigates feathering in a directly deposited pattern of organic material is disclosed. Deposition systems in accordance with the present disclosure include an evaporation source, an electrically conductive shadow mask, and an electrically conductive field plate. The source imparts a negative charge on vaporized organic molecules as they are emitted toward a target substrate. The source and substrate are biased to produce an electric field having field lines that extend normally between them. The shadow mask and field plate are located between the source and substrate and each functions as an electrostatic lens that directs the charged vapor molecules toward propagation directions aligned with the field lines as the charged vapor molecules approach and pass through them.

Abstract: An organic electroluminescent element includes, in order, a first electrode, an organic layer that includes an organic electroluminescent layer, an interface adjustment layer, a resistive layer, and a second electrode. The resistive layer has a specific resistance higher than a specific resistance of the second electrode. The interface adjustment layer has a specific resistance higher than the specific resistance of the second electrode and lower than the specific resistance of the resistive layer.

Abstract: In a method for fabricating an electronic device including a semiconductor memory, the method includes: forming stack structures, each of the stack structures including a variable resistance pattern; forming capping layers on the stack structures, the capping layers including an impurity; forming a gap fill layer between the stack structures; and removing the impurity from the capping layers and densifying the gap fill layer by irradiating the capping layers and the gap fill layer with ultraviolet light.

Abstract: A semiconductor device includes a first active structure on a substrate including a first epitaxial pattern, a second epitaxial pattern and a first channel pattern between the first epitaxial pattern and the second epitaxial pattern, the first channel pattern including at least one channel pattern stacked on the substrate. A first gate structure is disposed on top and bottom surfaces of the first channel pattern. A second active structure on the substrate and includes the second epitaxial pattern, a third epitaxial pattern and a second channel pattern between the second epitaxial pattern and the third epitaxial pattern in the first direction. The second channel pattern includes at least one channel pattern stacked on the substrate. The number of stacked second channel patterns is greater than the number of stacked first channel patterns. A second gate structure is disposed on top and bottom surfaces of the second channel pattern.

Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.

Abstract: Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer.

Abstract: A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.

Abstract: A flexible display device includes: a substrate including a main area, a first edge area arranged in a first direction with respect to the main area and including a first data pad portion, and a second edge area arranged in a second direction, which intersects the first direction, with respect to the main area and including a second data pad portion; and a flexible film on which first and second signal pad portions connected to the first and second data pad portions, respectively, are arranged. The first edge area may be bent along a first bending line, which extends in the second direction, and the second edge area may be bent along a second bending line, which extends in the first direction.

Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.

Abstract: A copper lead frame used in the assembly of a semiconductor device includes a die flag and lead fingers extending away from the die flag. Each lead finger has a proximal end near the die flag and a distal end further away from the die flag. Metal plating is formed on the lead fingers, where first lead fingers have the metal plating on their proximal ends and second lead fingers have the metal plating on their distal ends. The first and second lead fingers are arranged alternately around the die flag.

Abstract: A resistor for dynamic random access memory includes a substrate with a memory cell region and a peripheral region defined thereon, and a resistor formed on a shallow trench isolation of the substrate, wherein the resistor is provided with a winding portion and terminal portions at two ends of the winding portion. The winding portion is electrically connected with an overlying metal layer through contacts, and the terminal portion includes a polysilicon layer and a metal multilayer from the bottom up.

Abstract: A manufacturing method of a chip package includes the following steps. A light transmissive substrate is bonded to a first surface of a wafer, such that a dam element between the light transmissive substrate and the wafer covers a conductive pad of the wafer. A second surface of the wafer facing away from the first surface is etched, such that a hollow region and a trench selectively communicated with the hollow region are synchronously formed in the wafer. A first isolation layer on the conductive pad is etched to expose the conductive pad through the hollow region.

Abstract: An imaging device includes: a semiconductor substrate; a first pixel including: a first photoelectric converter above the semiconductor substrate, including first and second electrodes and a first photoelectric conversion layer between the first and second electrodes, configured to convert incident light into first charge; and a first charge accumulation region in the semiconductor substrate, electrically connected to the second electrode; and a second pixel including a second photoelectric converter above the semiconductor substrate, including third and fourth electrodes and a second photoelectric conversion layer between the third and fourth electrodes, configured to convert incident light into second charge; and a second charge accumulation region in the semiconductor substrate, electrically connected to the fourth electrode.