Abstract: There is disclosed a liquid crystal display device including a liquid crystal display cell layer and a pair of polarizers arranged on the sides of respective outer surfaces of the display cell layer. The liquid crystal display device further includes a retardation compensation layer having an optical birefringence which is arranged on at least one side, in a direction of the thickness of the display cell layer and between the polarizers, which compensates a change in the retardation caused when light passes through the display cell layer so as to improve viewing angle characteristics. A direction of a maximum one of principal refractive indices of the retardation compensation layer is oriented in a direction substantially parallel to a direction of the normal perpendicular to the surfaces of transparent substrates of the display cell layer.

Abstract: A low power push pull off chip driver for differential cascode current circuitry is described that includes the collectors of a differential pair directly coupled to bases of a push pull driver and level shifters coupled to the input of the differential pair to prevent saturation of the differential pair.

Abstract: A clocking methodology for VLSI chips which uses global overlapping clocks plus locally or remotely generated non-overlapping clocks. Two overlapping clocks and two non-overlapping clocks are thus available in each block of a chip for use as timing edges. The global overlapping clocks are used where possible to provide timing advantages, while the non-overlapping clocks are used to eliminate race conditions as data propagates down a pipeline of transparent registers. Generally, one non-overlapping clock has an edge which must fall before a clock edge of the other non-overlapping clock rises and an edge which must rise after a clock edge of the other non-overlapping clock falls. These signals may be applied to adjacent stages to prevent race conditions; however, the "dead" time between the falling of one clock edge and the rising of the other clock edge has performance costs.

Abstract: An image clock signal generating system generates an image clock signal which is used to enable and disable a scan of an optical scanner, and comprises a phase locked loop (PLL) circuit for generating an image clock signal in response to a reference pulse signal which comprises a plurality of pulses during a time corresponding to a scan range of the optical scanner and no pulses during a time corresponding to a no-scan range of the optical scanner. The PLL circuit includes a phase comparator which receives the reference pulse signal and a feedback signal and outputs a phase error signal dependent on a phase error between the two signals, a voltage controlled oscillator (VCO) for outputting an image clock signal, and an initial phase matching circuit for outputting the feedback signal in response to the image clock signal output from the VCO.

Abstract: In this invention, animation effects have been obtained in a device containing a light source illuminating a linear polarizer (3) producing plane polarized light which is rotated in an electro-optical cell/cells (2) such as a modified TN or STN Liquid Crystal or PLZT cell. The angle of the plane is changed at the required speed by a voltage applied to the electrodes (6) of the cell; this voltage being generated in an electronic circuit (8) or obtained from the output of transducer or a manual voltage controller. The rotated plane polarized light is shining through a stationary set of at least two linear polarizers (1) placed side by side and oriented at different angles and then through a screen containing the art work (7). The emerging lighted image is perceived by the viewer (5) as a change or as an animated movement of the art work. Color effects can also be obtained when a seocnd electro-optical cell with a chromatic polarizer is used in a serial arrangement with the above device.

Abstract: A full color liquid crystal display comprises first, second, and third subtractive LCD filters, each filter comprising means for independently subtracting one of the primary subtractive colors from a polychromatic light beam, without substantially affecting the other subtractive colors. Each of the subtractive LCD filters combines wavelength selective dichroic polarizers with a twisted nematic liquid crystal cell to provide a filter that can selectively subtract varying amounts of incident spectral radiant energy from within one of three primary energy bands. A first selective polarizer that linearly polarizes wavelengths in the appropriate one of the above mentioned color bands, while passing light in the other two bands substantially unaffected, a first liquid crystal cell, and a second selective dichroic polarizer identical to the first polarizer, but positioned wih its axis of polarization perpendicular to that of the first polarizer.

Abstract: A clock switching apparatus includes a first phase synchronizing part for receiving n (n is an integer) input clock signals and for generating n first clock signals respectively related to the n input clock signals. Each of the n first clock signals has a frequency higher than that of a corresponding one of the n input clock signals. A selector selects one of the n first clock signals. A frequency divider generates a second clock signal obtained by frequency-dividing the one of the n first clock signals selected by the selector. A second phase synchronizing part generates an output clock signal synchronized with the second clock signal.

Abstract: An input signal is received by a level shift circuit to generate a plurality of level-shifted output signals which have different shift amounts to each other. A switch circuit, selectively outputs the level-shifted output signals in response to a logic level of the input signal. The switch circuit selects a signal having a higher potential from the level-shifted output signals when the logic level of the input signal indicates a first level, and selects a signal having a lower potential from the level-shifted output signals when the logic level of the input signals indicates a second level.

Abstract: An output circuit comprises first and second transistors connected in series between a first voltage source and an second voltage source such that the first and second transistors are turned on and turned off respectively in response to an input logic signal and a logic inversion thereof, third and fourth transistors connected in series between a third voltage source and fourth voltage source such that the third and fourth transistors are turned on and turned off respectively in response to the logic inversion of the input logic signal and the input logic signal, first and second power transistors connected in series between a fifth voltage source and a sixth voltage source such that the first power transistor is turned on in response to the turning-on of the first transistor and turned off in response to the turning-on of the second transistor, the second power transistor is turned on in response to the turning-on of the third transistor and turned off in response to the turning-on of the fourth transistor,

Abstract: A dynamic logic gate includes a precharge device for precharging the logic gate in synchronism with a clock; a partial logic gate arranged such that, depending on the logic states of the logic inputs, current in allowed to flow between its two terminals or is cut off; a bipolar transistor whose emitter is grounded, and a discharge device for discharging the charge stored in the base of the bipolar transistor during the precharge period. The logic gate speeds up the logic operation by suddenly discharging the load capacity of the circuitry by supplying the conducting current of the partial logic gate to the bipolar transistor base and using the high speed current amplification action of the bipolar transistor.

Abstract: The present invention relates to a light shield for use in liquid crystal displays. According to the present invention, the light shielding layer includes an acrylic resin with a cross-linked structure in which carbon black particles are dispersed. Further, the light shield may be adapted to cover a switching element which controls the voltage applied to the liquid crystals. In addition, the present invention is directed to a method of manufacturing a light shield which includes an acrylic resin with cross-linked structure in which carbon black particles are dispersed.

Abstract: A displaying device having a liquid crystal display, a light source, and an illuminating member. The displaying device is provided with at least two light receiving portions for respectively receiving external light and the light emitted by the light source. The illuminating surface of the illuminating member is arranged to face the back surface of the liquid crystal display for illuminating the liquid crystal display from behind. A casing for fixedly accommodating the liquid crystal display, the light source, and the light transmitting member therein is provided. The external light and the light emitted by the light source is selectively or simultaneously received by the illuminating member to illuminate the back surface of the liquid crystal display.

Abstract: A data reproducing circuit for a memory system having a data sensing head includes a first equalizing circuit for correcting a shift of a position of a peak of a reproduction signal supplied from the data sensing head and for generating a first signal in which the shift of the position of the peak has been corrected, and a second equalizing circuit for correcting a variation in an amplitude of the reproduction signal supplied from the data sensing head and for generating a second signal in which the variation of the amplitude of the reproduction signal has been corrected. A peak position detecting circuit detects the position of the peak of the reproduction signal from the first signal supplied from the first equalizing circuit. An amplitude detecting circuit detects the amplitude of the reproduction signal from the second signal supplied from the second equalizing circuit.

Abstract: A sine wave synthesis controller circuit intended to be utilized in conjunction with a digitally-controlled neutral-point clamped inverter to produce a sinusoidal waveform from a direct current source. The controller circuit is configured so that it provides separate positive and negative control signals to the neutral-point clamped inverter's logic controller. These signals direct the modulation a sinusoidal waveform in response to a reference sine wave, the instantaneous voltage output by the neutral-point clamped inverter, as well as positive and negative reference voltages input to the controller.

Abstract: There is disclosed a driver circuit for driving a flat panel display. In this invention, a gate bias for a MOS transistor for charging an output terminal to high level is generated by a constant voltage element. The value of a current supplied to the constant voltage element is controlled by a current control circuit. In order to turn off the charging MOS transistor, a MOS transistor for discharging the node of the gate of the charging MOS transistor is set in an ON state. In order to switch an output, two drive signals are output from a drive signal generator to turn off both the charging MOS transistor for charging the output terminal to high level and the discharging MOS transistor for discharging the output terminal to low level.

Abstract: A circuit for modulating or demodulating an input potential includes a first operational amplifier for receiving the input potential and a second operational amplifier for outputting an output potential. A resistor network is connected to the operational amplifiers. A switch with a first position and a second position is connected to the resistor network and to at least one of the operational amplifiers. The circuit also includes a mechanism for repeatedly driving the switch between its first position and its second position. When the switch is in its first position, the output potential equals the input potential. When the switch is in its second position, the output potential equals minus one times the input potential.

Abstract: Electrical buffer output circuitry includes a first high branch having a high signal input terminal, a low input branch having a low input signal input terminal, and a signal output for the buffer circuitry. Either the high branch or the low branch is turned on in response to a signal at one of the input terminals, and the resistance of the turned on branch is varied as a function of time to improve the speed and noise characteristics of the buffer until the output voltage stabilizes.

Abstract: A peak detector circuit includes a switch for charging and discharging a capacitor at predetermined rates. In a first mode of operation, the switch is open and the peak detector functions to provide an output voltage that is indicative of the peak voltage level occurring at its input by charging a capacitor at a first predetermined rate. In a second mode of operation, the switch is closed and the peak detector functions to discharge the capacitor at a second predetermined rate and to a predetermined voltage. Subsequently in the second mode of operation, the peak detector then functions to provide an output voltage that follows its input voltage.

Abstract: An electrical signal filter composed of a pair of cascaded filter sections in which the group delays of the two filter sections are matched so that their non-linear effects cancel in the passband, resulting in an overall linear phase. In addition, the attenuation slope after the first null in one filter section's stopband response is complemented by the other filter's stopband attenuation. This prevents the overall stopband attenuation from falling to extremely low values as with some filters, which, in turn, limits the time domain overshoot. The passband group delay and stopband attenuation characteristics are controlled by appropriate selection of the passband ripple and filter order number parameters of the filter. In a preferred embodiment, the two filter sections are of the elliptic and Chebyschev type. The invention can be implemented as analog-component active filter circuit or as a digital filter.

Abstract: A phase detector circuit is provided for correction of operation of a synchronous delay line clock generator. The phase detector includes multiple edge detectors. The multiple edge detectors provide an override of any corrective action by the rest of the phase detector to the synchronous delay line output, notwithstanding presence or absence of any phase error of less than 360.degree., if the phase position of the delay line output signal is off by an integral multiple of 360.degree.. Multiple taps from daisy-chained or series-connected delay line elements are provided to the multiple edge detectors. The multiple edge detectors compare the edge produced by each such tap against (in the first instance) one division of divided clock signal or (for each subsequent tap) the result of the previous such comparison. In each such case, the comparison is accomplished by a not R, not S flip-flop receiving the signals to be compared.