Patents Examined by Stanley Tso
  • Patent number: 11705390
    Abstract: Embodiments disclosed herein include electronic packages with improved differential signaling architectures. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises alternating metal layers and dielectric layers. In an embodiment, a first trace is embedded in the package substrate, where the first trace has a first thickness that extends from a first metal layer to a second metal layer. In an embodiment, the electronic package further comprises a first ground plane laterally adjacent to a first side of the first trace, and a second ground plane laterally adjacent to a second side of the first trace.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: July 18, 2023
    Assignee: Intel Corporation
    Inventors: Andrew Collins, Arghya Sain
  • Patent number: 11699632
    Abstract: Methods for attachment and devices produced using such methods are disclosed. In certain examples, the method comprises disposing a capped nanomaterial on a substrate, disposing a die on the disposed capped nanomaterial, drying the disposed capped nanomaterial and the disposed die, and sintering the dried disposed die and the dried capped nanomaterial at a temperature of 300° C. or less to attach the die to the substrate. Devices produced using the methods are also described.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: July 11, 2023
    Assignee: ALPHA ASSEMBLY SOLUTIONS INC.
    Inventors: Monnir Boureghda, Nitin Desai, Anna Lifton, Oscar Khaselev, Michael T. Marczi, Bawa Singh
  • Patent number: 11696393
    Abstract: A method for manufacturing a circuit board is disclosed. An inner wiring base board with a first opening is provided. A base board is fixed in the first opening, and a first wiring base board and a second wiring base board are pressed on opposite surfaces of the inner wiring base board. The base board is made of ceramic and has a high light reflectivity of 92% to 97%. A first conductor layer and a second conductor layer are formed on opposite surfaces of the laminated structure. The first conductor layer includes a plurality of connecting pads on the base board. A solder mask is formed on an outer side of the first conductor layer, the solder mask has a high light reflectivity of 92% to 95%, and the base board is exposed outside the solder mask.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: July 4, 2023
    Assignees: QING DING PRECISION ELECTRONICS (HUAIAN) CO., LTD, Avary Holding (Shenzhen) Co., Limited.
    Inventors: Jin-Cheng Wu, Mei-Hua Huang, Ning Hou, Hua-Ning Wang, Qiang Song, Rong-Chao Li
  • Patent number: 11683880
    Abstract: Encapsulated PCB assembly (1) for electrical connection to a high- or medium-voltage power conductor in a power distribution network of a national grid, comprising a) a PCB (10), delimited by a peripheral edge (20) and comprising a high-tension pad (60, 62) on a voltage of at least one kilovolt, b) an electrically insulating encapsulation body (70) in surface contact with, and enveloping, the high-tension pad and at least a portion of the PCB edge adjacent to the high-tension pad, c) a shielding layer (80) on an external surface (90) of the encapsulation body and for being held on electrical ground or on a low voltage to shield at least a low-voltage portion of the PCB. The high-tension pad extends to the peripheral edge of the PCB.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: June 20, 2023
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Gunther A. J. Stollwerck, Mark Gravermann, Jens Weichold, Sebastian Eggert-Richter, Michael H. Stalder
  • Patent number: 11657964
    Abstract: A multilayer capacitor includes a capacitor body including an active region having dielectric layers and internal electrodes alternately stacked therein, the capacitor body including upper and lower covers disposed on upper and lower surfaces of the active region, respectively; and an external electrode disposed on an external surface of the capacitor body. In one of the upper and lower covers, a portion thereof between a boundary surface of the active region and a boundary surface of the capacitor body is divided into a first cover region adjacent to the active region and a second cover region adjacent to the boundary surface of the capacitor body, and the first cover region includes grains having a core-shell structure doped with Sn. The first cover region includes 20% or more of Sn-doped core-shell structure grains, compared to the total of grains in the first cover region.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: May 23, 2023
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Chun Hee Seo, Jong Suk Jeong, Jin Woo Kim, Tae Hyung Kim, Jeong Wook Seo, Dong Geon Yoo, Jong Hoon Yoo, Su Been Kim
  • Patent number: 11659665
    Abstract: A connection structure-embedded substrate includes: a printed circuit board including a plurality of first insulating layers of which at least one has a cavity provided therein, a plurality of first wiring layers disposed as at least one of an outer portion and an inner portion of the plurality of first insulating layers, and a first build-up insulating layer disposed on an upper surface of the plurality of first insulating layers; and a connection structure at least partially disposed in the cavity. The first build-up insulating layer is disposed in the cavity, and each of a lower surface of the connection structure and a lower surface of the cavity is in contact with at least a portion of the first build-up insulating layer, respectively.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: May 23, 2023
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ho Hyung Ham, Won Seok Lee, Jae Sung Sim
  • Patent number: 11651874
    Abstract: High-voltage insulators are disclosed that are capable of handling diverse requirements, such as providing high standoff voltages, high temperature cycling, and the ability to withstand flexural stress. One high-voltage insulator includes a first piece formed from a first material, a second piece formed from a second material, and an interface section where the first piece contacts with and forms a seal with the second piece. The interface includes a first groove located that accommodates a first gasket, sets of matching threads on the first and second pieces. The interface section further accommodates a second gasket. In this multi-piece high-voltage insulator, the first material can have a first set of flexural, heat resistance, and electrical standoff characteristics suitable for a first environment, and the second material can have a second set of flexural, heat resistance and electrical standoff characteristics suitable for a second environment.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: May 16, 2023
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Yuri Anatoly Podpaly, Michael Gordon Anderson, Steve Hawkins, Alexander Peter Povilus, Chris Vice
  • Patent number: 11646479
    Abstract: A method for producing a waveguide in a multilayer substrate involves producing at least one cutout corresponding to a lateral course of the waveguide in a surface of a first layer arrangement comprising one or a plurality of layers. A metallization is produced on surfaces of the cutout. A second layer arrangement comprising one or a plurality of layers is applied on the first layer arrangement. The second layer arrangement comprises, on a surface thereof, a metallization which, after the second layer arrangement has been applied on the first layer arrangement, is arranged above the cutout and together with the metallization on the surfaces of the cutout forms the waveguide.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: May 9, 2023
    Assignee: Infineon Technologies AG
    Inventor: Markus Josef Lang
  • Patent number: 11647592
    Abstract: A system for effectively curing dry film ink throughout its thickness on circuit boards being made applies an exposure system, a circuit board, and a method for making the circuit board. The exposure system includes a plurality of mixed light sources with different wavelengths within a range of 365 nm to 440 nm, the mixed light sources can output at least three different wavelengths of light each of substantially a single wavelength and a fourth source of light able to output light of a spectrum of wavelengths, the ranges of light being between 365 nm and 440 nm.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: May 9, 2023
    Assignees: QING DING PRECISION ELECTRONICS (HUAIAN) CO., LTD, Avary Holding (Shenzhen) Co., Limited.
    Inventors: Ching-Lung Chuang, I-Hsin Chen, Li-Jen Chang
  • Patent number: 11640877
    Abstract: An electronic component includes: a multilayer capacitor including a capacitor body and first and second external electrodes respectively disposed on opposing end surfaces of the capacitor body; and an ESD member disposed on a first side surface of the multilayer capacitor perpendicular to a mounting surface of the multilayer capacitor, such that the ESD of the multilayer capacitor may be effectively controlled.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: May 2, 2023
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Heung Kil Park, Gu Won Ji, Sang Soo Park
  • Patent number: 11640860
    Abstract: A circuit module includes an interposer, and the interposer includes an element body including a first surface, a first interposer terminal provided on the first surface of the element body, and connected to a first external element, a second interposer terminal provided on the first surface of the element body, and connected to a second external element, a first wiring provided in the element body, and electrically connecting the first interposer terminal and the circuit board with each other, a second wiring provided in the element body, and electrically connecting the second interposer terminal and the circuit board with each other, and a bypass wiring provided in the element body and/or on a surface of the element body, and electrically connecting the first interposer terminal and the second interposer terminal with each other.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: May 2, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Keito Yonemori, Hirokazu Yazaki, Takanori Tsuchiya
  • Patent number: 11640863
    Abstract: The disclosure relates to a glass-metal feedthrough, composed of an outer conductor or a basic body, a glass material or glass-ceramic material, and an inner conductor. The inner conductor is preferably a metal pin and the inner conductor is sealed in the outer conductor, in particular basic body, in the glass or glass-ceramic material. The metal pin comprises a material with high conductivity and/or low contact resistance, as well as a sleeve element that surrounds the metal pin at least partially.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: May 2, 2023
    Assignee: SCHOTT AG
    Inventors: Robert Hettler, Wee Kiat Chai, Rainer Graf
  • Patent number: 11638351
    Abstract: A component-embedded substrate includes: insulating layers each including a wiring pattern; an embedded component including a connection terminal; a plurality of vias that electrically connect the connection terminal to the wiring patterns adjacent to each other in a lamination direction. Each of the vias is composed of a via hole in the insulating layer and a conductive material in the via hole. One of the vias is a connection via connected to the connection terminal, and another of the vias is an adjacent via adjacent to the connection via in the lamination direction. The connection via and adjacent via overlap in a plan view. S1/A1?0.61 and S1/A2?0.61 are satisfied, where A1 is an average cross-sectional area of the connection via, A2 is an average cross-sectional area of the adjacent via, and S1 is an overlapping area of the connection via and adjacent via in the plan view.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: April 25, 2023
    Assignee: Fujikura Ltd.
    Inventors: Masakazu Sato, Nobuki Ueta, Yoshio Nakao, Masatoshi Inaba
  • Patent number: 11631542
    Abstract: An electronic component includes an element body having a dielectric and an inner electrode. The electronic component also includes at least one external electrode. Each external electrode includes a base layer, a plating layer and a covering layer. The base layer is formed on a plurality of surfaces of the element body to have a plurality of faces facing different directions. The base layer is connected to the inner electrode, and contains a metal. The plating layer is formed on a mounting face of the base layer and on a side face of the base layer to which the inner electrode is connected. The covering layer is formed on at least a portion of a face of the base layer, which is opposite to the mounting face of the base layer. A surface of the covering layer is less wettable than a surface of the plating layer by solder.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: April 18, 2023
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Kiyoshiro Yatagawa, Satoshi Kobayashi, Ryosuke Hoshino
  • Patent number: 11627666
    Abstract: An electronic device is provided, the electronic device includes a driving substrate (13), the driving substrate includes a plurality of circular grooves and a plurality of rectangular grooves, and a plurality of disc-shaped electronic components, at least one disc-shaped electronic component is disposed in at least one circular groove, an alignment element positioned on a top surface of the at least one disc-shaped electronic component, a diameter of the at least one disc-shaped electronic component is defined as R, a diameter of the alignment element is defined as r, a width of at least one rectangular groove among the rectangular grooves is defined as w, and a height of the at least one rectangular groove is defined as H, and the disc-shaped electronic component and the rectangular groove satisfy the condition of (R+r)/2>(w2+H2)1/2.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: April 11, 2023
    Assignee: InnoLux Corporation
    Inventor: Chun-Hsien Lin
  • Patent number: 11626247
    Abstract: An electronic component includes an element body and external electrodes. The element body includes a dielectric and an internal electrode. Each of the external electrodes includes a base layer formed on multiple surfaces of the element body and an electrically-conducting material layer formed on the base layer, the base layer including a metal and co-material particles dispersed in the metal and being connected to the internal electrode. The co-material particles at an interface surface between the base layer and the electrically-conducting material layer have edges covered with the metal at the interface surface. The electrically-conducting material layer is in contact with the co-material particles at the interface surface and the metal covering the edges of the co-material particles at the interface surface.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: April 11, 2023
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Junichi Shinozaki, Toshiki Kondo, Ryosuke Hoshino, Takahisa Fukuda
  • Patent number: 11622449
    Abstract: In a multilayer ceramic capacitor, an interposer includes, on a side of a first external electrode in a length direction, a first through hole that penetrates the interposer in a stacking direction, and provides electrical conduction between a first joining electrode and a first mounting electrode. The first through hole further includes a first metal film provided on an inner wall thereof. The interposer includes, on a side of a second external electrode in the length direction, a second through hole that penetrates the interposer in the stacking direction, and provides electrical conduction between a second joining electrode and a second mounting electrode. The second through hole further includes a second metal film provided on an inner wall thereof.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: April 4, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Satoshi Yokomizo
  • Patent number: 11616351
    Abstract: An electrical box having an enclosure and a conduit hub adapter that is configured to engage a portion of the enclosure. The enclosure defines an opening that is configured to receive an electrical power conductor. The conduit hub adapter is movable with respect to the enclosure from a disengaged position to an engaged position. A retainer may be positioned adjacent the opening to engage the conduit hub adapter when in the engaged position and secure the conduit hub adapter to the enclosure. The conduit hub adapter may be configured for engagement with the enclosure in a single orientation. The retainer may be configured so that it may only be disengaged from the conduit hub adapter from within an interior space of the enclosure. The enclosure may have a second opening with a second conduit hub adapter configured to engage the enclosure adjacent the second opening.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: March 28, 2023
    Assignee: MILBANK MANUFACTURING CO.
    Inventors: Brian Hagen, Shawn Glasgow, William E. McCarthy, Justin Haesemeier
  • Patent number: 11610728
    Abstract: An electronic component comprising a glass body containing a photosensitizer; a conductor as at least a part of an electric element, arranged on the glass body; a terminal electrode as a terminal of the electric element, arranged above an outer surface of the glass body, with the terminal electrode being electrically connected to the conductor; and an insulating film arranged above the outer surface of the glass body. The insulating film reflects or absorbs light in a photosensitive wavelength range of the photosensitizer contained in the glass body.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: March 21, 2023
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yoshitaka Matsuki, Hiraku Kawai, Yuichi Iida, Masahiro Kubota, Fumihiko Naruse
  • Patent number: 11598911
    Abstract: Embodiments described herein relate to a system for positioning indicator lights of a network device. The system may include a circuit board, which may include a circuit board edge positioned behind a front panel of the network device, two surfaces; and a side of the circuit board edge positioned between the two surfaces. The system may also include a hole through the circuit board near the circuit board edge, a cutout extending from a portion of the hole to the side of the circuit board edge, a LED coupled to the surface of the circuit board and adapted to emit light into the hole, and a lightpipe disposed in the hole to receive light emitted from the LED into a first end of the lightpipe. The lightpipe may direct the light from a second end of the lightpipe toward an opening in the front panel of the network device.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: March 7, 2023
    Assignee: Arista Networks, Inc.
    Inventors: Matthew Albert Moe, Robert Morris Wilcox, Richard Neville Hibbs, Tiong Khai Soo, Xing Wang, James Dennis MacDonald, Clifford Bryant Willis