Abstract: In one or more embodiments, one or more systems, methods, and/or processes may query information handling systems (IHSs) for respective power consumption levels; may determine an amount of power utilized by the IHSs from the power consumption levels; may determine an integer number of power supply units (PSUs) based at least on the amount of power utilized by the IHSs; may determine that a number of operational PSUs changes; may determine that the number of operational PSUs is not at or above a threshold number; may determine if the number of operational PSUs is at or above the integer number of PSUs; if the number of operational PSUs is at or above the integer number of PSUs, may determine that the number of operational PSUs changes; and otherwise, may provide throttle down information to the IHSs.

Abstract: A method for activating a processing unit using a circuit configuration in response to an activation signal, and when the activation signal exceeds a switching threshold, a reference-voltage source is connected to a supply-voltage source, the reference-voltage source supplies a first reference voltage at a first comparator and supplies a second reference voltage at a second comparator, the first comparator carries out a comparison with the first reference voltage in order to detect a high level of the activation signal, and the second comparator carries out a comparison with a second reference voltage, and if a high level of the activation signal is detected, a voltage supply is activated with a time delay at a particularly low deviation from the desired delay time, via a variation of the supply voltage and the temperature.

Abstract: An adjustable performance boot system includes a processing system and an SPI memory storing firmware volumes. The processing system retrieves, via an SPI interface at a first SPI interface performance level, a first firmware volume including a first hash value generated using a second firmware volume. The processing system then increases the SPI interface performance level, retrieves the second firmware volume via the SPI interface at the increased SPI interface performance level, generates a second hash value using that second firmware volume and, in response to it not matching the first hash value, lowers the SPI interface performance level. The processing system then retrieves the second firmware volume via the SPI interface at the decreased SPI interface performance level, generates a third hash value using that second firmware volume and, in response to it matching the first hash value, uses that second firmware volume to provide a BIOS.

Abstract: In an embodiment, a system may support a “coast mode” in which the power management unit (PMU) that supplies the supply voltage to an integrated circuit is disabled temporarily for certain modes of the integrated circuit. The integrated circuit may continue to operate, consuming the energy stored in capacitance in and/or around the integrated circuit. When coast mode is initiated, a time interval for coasting may be determined. When the time interval expires, the PMU may re-enable the power supply voltage.

Abstract: Methods and apparatus for synchronization of time between independently operable processors. Time synchronization between independently operable processors is complicated by a variety of factors. For example, neither independently operable processor controls the other processor's task scheduling, power, or clocking. In one exemplary embodiment, a processor can initiates a time synchronization process by disabling power state machines and transacting timestamps for a commonly observed event. In one such embodiment, timestamps may be transferred via inter-processor communication (IPC) mechanisms (e.g., transfer descriptors (TDs), and completion descriptors (CDs)). Both processors may thereafter coordinate in time synchronization efforts (e.g., speeding up or slowing down their respective clocks, etc.).

Abstract: An information processing apparatus for performing hibernation startup is provided. The information processing apparatus includes a selecting unit that selects snapshot creation startup or snapshot startup; a startup unit that initiates startup processes of one or more applications when the snapshot creation startup is selected; the applications, which send notifications after the startup processes have progressed to respective points in time for snapshot creation; a creation instructing unit that sends an instruction to create a snapshot after receiving the notifications from all the applications; a creating unit that creates the snapshot based on the instruction; a memory that stores the snapshot; and a startup instructing unit that reads the snapshot stored in the memory when the snapshot startup is selected, and sends, to the applications, an instruction to resume the startup processes subsequent to the respective points in time, so as to complete the startup processes of the applications.

Abstract: A computer architecture suitable for out-of-order processors manages the problem of timing slack, in which an instruction completes before its clock cycle, by recycling that slack to allow the next succeeding instruction allowing that instruction to begin execution earlier. This recycling mechanism is enabled through the use of a transparent gating between execution units which allows data transfer before clock cycle boundaries and, in some cases, by aggressively issuing children instructions contemporaneously with their parent instruction after a grandparent instruction is issued.

Abstract: The present disclosure provides a data communication device and a data communication system. The data communication device includes a power supply interface coupled to a direct current power supply, a wired communication interface, a main control chip, and an energy storage component. The data communication system includes a master communication device and a slave communication device.

Abstract: A method for runtime optimization of a configurable processing architecture are disclosed. The method comprises receiving a plurality of calls for running at least one function; identifying at least one pattern among the plurality of received calls; and based on the at least one pattern, manipulating at least a portion of the configurable processing architecture, to compute the least one function.

Abstract: According to various examples of the present invention, a wearable electronic device comprises: an energy harvester for generating electric energy on the basis of a movement or a change in the shape of the wearable electronic device; a first processor for controlling the energy harvester; a first sensor and a second sensor; and a second processor for controlling the first sensor and the second sensor, wherein the first processor transmits, to the second processor, a control signal for transitioning the second processor into an activated state if the electric energy generated by the energy harvester satisfies a designated first condition, and the second processor can be set such that first sensor data is acquired through the first sensor and second sensor data is selectively acquired from the second sensor according to whether the first sensor data satisfies a designated second condition, when the second processor is transitioned from an inactivated state to the activated state by responding to the control sig

Abstract: Technology for a system operable to extend a level of processor performance is disclosed. The system can comprise a power source connected to a platform voltage regulator (VR) and one or more processors and configured to provide an input power to the platform VR. The system can further comprise the platform VR connected to a peripheral interface and the one or more processors and configured to power the peripheral interface and send a power good signal to the one or more processors. The system can further comprise the peripheral interface connected to the platform VR and the one or more processors and configured to connect to a peripheral device and send a signal to the one or more processors when a peripheral interface connection state is identified as connected.

Abstract: Systems and methods for time synchronization for clocks separated by a communication link allow a master clock to be positioned at a downstream-facing port or an upstream-facing port and to send synchronization commands with an associated time stamp embedded in transport layer protocol (TLP) prefixes to a slave clock. The slave clock may update its time value based on the received time stamp. Further, the slave may calculate a round trip delay between the master clock and the slave clock and use this delay calculation to correct the slave clock. The delay calculation may likewise be made using TLP prefixes. By using TLP prefixes in this fashion, the time synchronization can piggyback on existing message traffic, which reduces signaling overhead. Likewise, by using the TLP prefixes, the time synchronization may be initiated from either an upstream-facing port or a downstream-facing port.

Abstract: A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

Abstract: A power control circuit includes a first power supply circuit configured to supply power to a universal serial bus upon a motherboard is turned on. When the motherboard is turned on, a first power source outputs a first voltage to a first input terminal of a double diode of the first power supply circuit, a second power source outputs a second voltage to a second input terminal of the double diode, an output terminal of the double diode outputs a first voltage, the first voltage controls the first electronic switch to switch on, and a third power supply outputs a second voltage through a first electronic switch of the first power supply circuit to provide power to the universal serial bus.

Abstract: An electronic device according to various embodiments may include a first connector including at least one first pin and at least one second pin configured to be connected to an external electronic device; a second connector comprising at least one third pin and at least one fourth pin configured to be connected to a power supply; a switching circuit; and a processor electrically connected to the first connector, the second connector, and the switching circuit, wherein the processor is configured to determine a connection with the external electronic device or a connection with the power supply, and the processor is set to cause, when connected to the external electronic device via the first connector and connected to the power supply via the second connector, power received from the power supply via the at least one third pin to be supplied to the at least one first pin using the switching circuit.

Abstract: A method is provided for operating an electrical device (14) which has an operating mode and a sleep mode, in which method an oscillator apparatus (20) provides a first analog signal (f(t)) with a first frequency and second analog signal (f?(t)) with a second frequency, wherein the second analog signal (f?(t)) is different from the first analog signal (f(t)), a comparator apparatus (28) compares the first analog signal (f(t)) and/or second analog signal (f?(t)) with at least one reference value (Uref) or a reference value range, and an interrupt signal for transferring from the sleep mode into the operating mode is produced if a certain comparison result is detected.

Abstract: A wireless mobile device (“UE”) operating in a battery-conserving low-power state processes incoming signaling or data in a received message to determine whether to act further on information in the message by enabling additional processing capability in the UE. A server may generate awaken information derived from a stored secret value that only the UE device and a server that manages the UE can obtain. The awaken information may also be based on a shared value shared between the server and the UE. The UE may separately derive the awaken information and may exit a low power state when awaken information received from the server in an awaken message in a first protocol matches the separately derived awaken information. The server may transmit a fall-back second awaken message in a different protocol than the first protocol if no confirmation is received that the UE received the first awaken message.

Abstract: A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

Abstract: This disclosure provides a hardware structure of a trusted computer, which comprises: a trusted socket and a trusted module compatible with TPM and TPCM specifications; a trusted management module connected to the trusted socket for measuring the credibility; a firmware memory of BIOS connected to the trusted socket. A firmware memory of BMC connected to the trusted socket through a switch module. When the trusted management module is in the standby status, the trusted management module measures the credibility of the firmware memory of the BIOS and the firmware memory of the BMC according to the output signal of the trusted module inserted to the trusted socket, and the computer is allowed being turning on as the measurement is pass. This disclosure further relates to a trusted booting method for a computer.

Abstract: Embodiments of the disclosure provide a method and apparatus for controlling a startup bootstrap program of an intelligent TV set, and relate to the field of an embedded system so as to shorten a period of time for startup boot while initializing a screen normally. In the disclosure, after a system is powered on, a first task of initializing a screen in a startup bootstrap program is executed, and the length of preset time required for executing the first task is obtained, wherein the startup bootstrap program is a bootstrap program for initializing pieces of software/hardware of the system; executing a second initialization task unrelated to initializing the screen in the startup bootstrap program is executed while the first task is being executed, thus addressing the problem in the related art.