Abstract: The present disclosure relates to systems, methods, and computer readable media for enabling a power shelf unit to communicate a power throttle signal to devices of a power rack (or other grouping of devices) via a busbar. In particular, systems disclosed herein involve detecting a trigger condition associated with throttling power on server devices of a server rack. In response to detecting the trigger condition, systems here cause a direct current (DC) power supply voltage to change from an operating voltage to a notification voltage for a period of time to alert or otherwise communicate to server devices coupled to the busbar of the trigger condition. Causing the DC power supply voltage to change to the notification voltage may cause processors on server devices to throttle power consumption in accordance with one or more power capping policies implanted thereon.

Abstract: An electronic device includes a main circuit including a processor, a sub circuit that transits between a first state and a second state, and a power supply circuit that supplies electric power to the main circuit and the sub circuit. An electrical distance between the main circuit and the power supply circuit is shorter than an electrical distance between the main circuit and the sub circuit. When the processor determines to cause the sub circuit to transit from the second state to the first state, the processor increases electric power supplied from the power supply circuit to the sub circuit. The sub circuit transits from the second state to the first state in response to increase of the electric power supplied from the power supply circuit.

Abstract: A system includes a power sourcing equipment (PSE) unit. The PSE unit includes a plurality of network ports. The PSE unit also includes a PSE board coupled to the plurality of network ports and configured to provide power to a plurality of powered devices (PDs) external to the PSE unit via respective network ports. The PSE unit also includes a sensing circuit configured to determine a power consumption parameter for the PSE board. The PSE unit also includes a controller configured to change a power state for at least one of the plurality of network ports based at least in part on the power consumption parameter.

Abstract: A method comprises predicting, based on corresponding historical workload data, a change in virtual network function demand during a future workload period, wherein the virtual network function is supported by a node. The method further comprises determining a target clock speed of one or more physical CPU cores of one or more processors of one or more servers in the node corresponding to the change in the virtual network function demand and adjusting the CPU CORE of the node to the target clock speed corresponding to the change in the virtual network function demand for the future workload period.

Abstract: An initial configuration query for an initial configuration query result is received from a service. The initial configuration query result comprises an executable configuration query engine that can be run by the service to serve one or more subsequent configuration query results to one or more subsequent configuration queries constrained by one or more immutable configuration constraints, wherein the initial configuration query comprises the one or more immutable configuration constraints. A subset of configuration data from a configuration database is selected based at least in part on the one or more immutable configuration constraints. The executable configuration query engine is generated, wherein the executable configuration query engine serves configuration data from the selected subset of configuration data.

Abstract: Power conservation logic for a storage node operates in parallel with an emergency shutdown process in which an emergency power source is engaged and data and metadata are destaged from volatile memory to non-volatile managed drives. The power conservation logic serially implements power conservation actions until enough reserve power is available to complete the emergency shutdown process. The power conservation logic may learn how much power savings are realized from each conservation action and adjust the order in which the conservation actions are serially implemented, e.g. in order from greatest to least power consumption reduction.

Abstract: A method of generating an optimized executable configuration query engine is disclosed. A set of one or more immutable configuration parameters associated with a configurable service or a configurable application is received. At least a portion of a set of configuration data in a configuration database and at least a portion of the set of one or more immutable configuration parameters are transformed into a set of data and code in a compiler-readable format. An optimized subset of the set of configuration data in the configuration database is selected based at least in part on the set of one or more immutable configuration parameters. An optimized executable configuration query engine is generated based at least in part on the set of one or more immutable configuration parameters, wherein the optimized executable configuration query engine serves configuration data from the selected optimized subset of the set of configuration data.

Abstract: A data handoff controller includes a counter coupled to supply a count value indicative of a skew between a first clock signal and a second clock signal. The first and second clock signal have a fundamental beat frequency. A greatest common factor circuit is used to determine the fundamental beat frequency and the second is reset based on the beat frequency. A sampling circuit samples first clock domain data with the second clock signal. The sampling circuit is controlled to sample, at least in part, based on the count value. The count value can be used to impose a blackout window in which data is not sampled to avoid sampling data around data transitions of the first clock domain data. The count value can also be used to select an edge of the second clock signal to use for sampling the first clock domain data to ensure first clock domain data is not sampled during data transitions.

Abstract: A device interoperability system for one or more user devices associated with a user, wherein said one or more user devices comprises a first user device, said device interoperability system comprising a communications module, wherein a first connection is established between said first user device and said communications module; storage associated with said device interoperability system and coupled to said communications module, wherein said storage stores an operating system, one or more programs, and data associated with the user, further wherein said operating system is booted by said first user device via said first connection; and one or more processors to support said device interoperability system.

Abstract: In this method for controlling a server cluster, the cluster Including a plurality of nodes, automated agents measure the change in at least one metric quantifying the use of the nodes for the execution of an application, the agents determine, for each node, by measuring the metric, whether a change of phase has taken place in the executed application, and cause a change of the operation of the node if necessary; at regular intervals, an automated coordinator aggregates the metric measurements and the changes of operation of the nodes that have taken place and, on the basis of the aggregated measurements, the coordinator sends instructions to at least one of the agents.

Abstract: Methods and apparatus to dynamically throttle compute engines are disclosed. A disclosed example apparatus includes one or more compute engines to perform calculations, where the one or more compute engines are to cause a total power request to be issued based on the calculations. The example apparatus also includes a power management unit to receive the total power request and respond to the total power request. The apparatus also includes a throttle manager to adjust a throttle speed of at least one of the one or more compute engines based on comparing a minimum of the power request and a granted power to a total used power of the one or more compute engines prior to the power management unit responding to the total power request.

Abstract: Technologies for efficiently booting sleds in a disaggregated architecture include a sled. The sled includes a network interface controller, a set of processors, and firmware that includes an operating system. Additionally, the sled includes circuitry to perform, with multiple processors in the set of processors, a boot process. The circuitry is also to initialize the operating system present in the firmware, receive, with the network interface controller and from another sled, an assignment of a workload, and execute the assigned workload with the operating system.

Abstract: Systems and methods are disclosed method for controlling instantaneous current changes in parallel processors with arrays of parallel computing elements, such as neural processors. An exemplary method comprises monitoring the array of computing elements and determining a transition from a first activity level of the array to a second activity level of the array, such as an idle-to-active or active-to-idle transition. Once a transition is determined, the array is selectively controlled to minimize the instantaneous current change from the transition from the first activity level to the second activity level.

Abstract: Aspects of the embodiments are directed to systems, methods, and apparatuses for controlling power management states using a clock request message across a 3.3 volt GPIO pin. Systems can include a CPU root port to transmit to a platform controller hub (PCH) compliant with a PCIe protocol, a first clock request message, the first clock request message comprising a first bit set to assert a clock request transmit (CLKREQ TX assert) on a 3.3 volt general purpose input/output (GPIO) pin local to the PCH; detect that a connected device is entering into a power management state; and transmit, from the CPU root port, to the PCH, a second clock request message, the second clock request message comprising the first bit set to deassert the clock request transmit (CLKREQ TX deassert) and a second bit to assert a clock request protocol (CLKREQ#) on a 3.3 volt GPIO pin.

Abstract: A system may include a field-programmable gate array (FPGA). The FPGA may be configured to: determine a time corresponding to in which of x time periods a signal arrived at an input serializer based at least on a value; and determine a time when the signal arrived at an input pad based at least on a shift register latency value and the time corresponding to in which of the x time periods the signal arrived at the input serializer based at least on the value.

Abstract: An information handling system includes a BIOS ROM that stores a first firmware volume of BIOS code. A non-volatile memory device includes a first boot partition that stores a second firmware volume of the BIOS code. A processor executes the first and second firmware volumes during a Pre-EFI Initialization phase of a Unified Extensible Firmware Interface boot process.

Abstract: A method operates a first-in-first-out (FIFO) buffer with a first clock, and operates one of a read pointer or a write pointer of the FIFO buffer with the first clock while operating the other one of the read pointer or write pointer with a second clock. One of a serializer fed from the FIFO buffer output, or a de-serializer feeding the FIFO buffer input, is operated with the second clock. Timing pulses indicate that the pointer operating with the second clock has reached a predetermined point in its cycle. The phase of the second clock is adjusted based on a relationship between the timing pulses and an advance period of the pointer operating with the first clock. The pointer operating with the first clock is reset to achieve a desired value for the relationship. A skew created from adjusting the phase of the second clock is corrected.

Abstract: A power management system including a first circuit board, a second circuit board and a connection cable is provided. The connection cable is compatible with USB type-C specification and connects the first circuit board and the second circuit board. When the first circuit board determines that a first power state of the first circuit board changes, the first circuit board transmits the first signal to the second circuit board through a configuration channel (CC) terminal of the connection cable, the second circuit board changes a second power state of the second circuit board according to the first signal.

Abstract: An access point, which is a Power over Ethernet (PoE) Powered Device (PD) measures input voltage and input current. The access point determines a power requirement of the access point based on the measured current, measured voltage, and information about power requirements of access point components or devices coupled to the access point a power requirement of the access point. The access point communicates the determined power request to a power sourcing equipment (PSE), e.g., a network switch. In some embodiments, the access point further communicates one of: measured input current and measured input voltage to the PSE. The PSE uses the information received from the access point, e.g., power request and power measurements to determine an amount of power to be granted to the access point. If the access point does not receive the requested power level the access point selects internal components and/or external devices to de-power.

Abstract: In one embodiment, processor includes a first core to execute instructions, and a power controller to control power consumption of the processor. The power controller may include a hardware performance state controller to control a performance state of the first core autonomously to an operating system, and calculate a target operating frequency for the performance state based at least in part on an energy performance preference hint received from the operating system. Other embodiments are described and claimed.