Abstract: A functional safety POR system requires implementing voltage detectors and supervisory functions in a complex SOC. These features are implemented within the SOC without external components. Three stages of voltage monitoring are implemented to ensure redundancy.

Abstract: A display device includes: a display panel including scan lines, a first power line, a second power line, and pixels connected to the scan lines and the first and second power lines; a gate driver to sequentially provide scan signals to the scan lines based on a clock signal; and a power supply including transistors to convert an input power voltage into a first power voltage through a switching operation of the transistors and to supply the first power voltage to the first power line through a first output terminal. In response to an amount of current flowing through the pixels being less than a first reference current amount, the power supply is configured to change one or more of an off-duty of at least one of the transistors, a channel capacitance of at least one of the transistors, a switching frequency of at least one of the transistors, and a slew rate of at least one of control signals for the transistors.

Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification, The apparatus further includes a low power wake circuit configured to receive a low power wake signal and an identification information, and further configured to initiate a transition of the memory device from a low power state to an active state responsive to an active low power wake signal and the wake identification information matching the device identifier.

Abstract: Methods, systems, and devices for architecture-based power management for a memory device are described. Aspects include operating a first memory bank within a memory device in a first mode and a second memory bank within the memory device in a second mode. The memory device may receive a power down command for the first memory bank while operating the first memory bank in the first mode and the second memory bank in the second mode and switch the first memory bank from the first mode to a first low power mode while maintaining the second memory bank in the second mode. The first low power mode corresponds to less power consumption by the first memory bank than the first mode. In some cases, switching the first memory bank from the first mode to the first low power mode includes deactivating circuitry dedicated to the first memory bank.

Abstract: Methods and apparatus for synchronization of time between independently operable processors. Time synchronization between independently operable processors is complicated by a variety of factors. For example, neither independently operable processor controls the other processor's task scheduling, power, or clocking. In one exemplary embodiment, a processor can initiates a time synchronization process by disabling power state machines and transacting timestamps for a commonly observed event. In one such embodiment, timestamps may be transferred via inter-processor communication (IPC) mechanisms (e.g., transfer descriptors (TDs), and completion descriptors (CDs)). Both processors may thereafter coordinate in time synchronization efforts (e.g., speeding up or slowing down their respective clocks, etc.).

Abstract: Techniques are disclosed regulating an amount of power consumed by a server from a set of power supplies in which at least one power supply of the set is inactive. The power to a server, upon detecting that at least one power supply is inactive, is restricted based on a degree to which a power threshold value for the remaining power supplies is exceeded. The applied power reduction may be based on a proportion of a measurement interval during which an alert signal is received. The longer the alert signal is received by the system, the more server power consumption is reduced.

Abstract: An apparatus is provided which comprises: a first Power Management Unit (PMU); and a second PMU, wherein the first PMU is to manage transition of the apparatus from a low power state to a first active state, wherein the second PMU is to manage transition of the apparatus from the first active state to a second active state, and wherein the second PMU is to be powered down while the apparatus is to be in the low power state.

Abstract: An SCP boot system includes a chassis housing a BIOS and an SCP that presents a virtual BIOS boot media location to the BIOS. The SCP may receive a first physical boot media location from a management system and, when the SCP receives a first BIOS boot image retrieval request from the BIOS that is directed to the virtual BIOS boot media location, it retrieves a first BIOS boot image from the first physical boot media location and provides it to the BIOS. The SCP may then receive a second physical boot media location from the management system and, when the SCP subsystem receives a second BIOS boot image retrieval request from the BIOS that is directed to the virtual BIOS boot media location, it retrieves a second BIOS boot image from the second physical boot media location and provides it to the BIOS.

Abstract: A field-programmable gate array (“FPGA”) contains a configurable semiconductor organized in multiple clock regions with a clock fabric for facilitating user-defined logic functions. The clock fabric provides a set of regional clock signals (“RCSs”) generated from a clock source with a high clock signal quality (“CSQ”) for clocking logic blocks in a clock region. Also, a set of neighboring clock signals (“NCSs”) or inter-regional clock signals are generated from a neighboring clock source(s) for clocking logic blocks in two neighboring regions. In addition, the clock fabric is operable to provide secondary clock signals (“SCSs”) generated from the RCSs with a low CSQ for clocking logic blocks with less time-sensitive logic operations.

Abstract: This application relates to techniques that adjust the sleep states of a computing device based on user proximity detection procedures. The technique includes detecting a first pattern, using a first subset of sensors of one or more sensors coupled to the computing device, to determine if the object is proximate to the computing device. Provided the first pattern is not indicative of the object being proximate to the computing device, the technique detects a second pattern, using a second subset of sensors of the one or more sensors, to determine if the object is proximate to the computing device. Furthermore, provided either the first pattern or the second pattern is indicative of the object being proximate to the computing device and provided a first portion of a computer system within the computing device is operating within a low-power sleep state, the technique causes the first portion to enter into a high-power sleep state.

Abstract: Methods that can transition between multiple operating states are disclosed. One method includes monitoring an amount of power consumed by an information handling device operating in an idle state after transitioning from an active state to the idle state, transitioning an operating state of the information handling device to the active state in response to detecting that the amount of power consumed by the information handling device in the idle states exceeds a predetermined power consumption threshold value, and causing the operating state of the information handling device to transition back to the idle state subsequent to transitioning to the active state. Apparatuses and computer program products for performing the method are also disclosed.

Abstract: The present disclosure relates to systems and methods to maintain clock synchronization of multiple computers, or computer systems, through the exchange of communication messages that include clock and/or timing information.

Abstract: A BIOS platform configuration system includes a BIOS coupled to hardware subsystems. During initialization operations, the BIOS communicates with each of the hardware subsystems and retrieves respective hardware subsystem information that is associated with each of the hardware subsystems and that describes at least a portion of a communication route between that hardware subsystem and at least one other hardware subsystem. The BIOS then combines the respective hardware subsystem information that is associated with each of the hardware subsystems to generate configuration information that describes complete communication routes between each of the hardware subsystems, and configures at least one of the hardware subsystems using the configuration information.

Abstract: Embodiments of the present application relate to a method, apparatus, and system for waking up an app. The method includes adding an application (app) to a wake-up alarm group comprising a plurality of apps, adjusting a plurality of alarm wake-up times corresponding to the plurality of apps, wherein the plurality of alarm wake-up times corresponding to the plurality of apps are adjusted to be consistent, and waking up the plurality of apps belonging to the wake-up alarm group according to the adjusted alarm wake-up times corresponding to the plurality of apps belonging to the wake-up alarm group.

Abstract: The disclosed embodiments provide a system that operates a computer system. During operation, the system detects a first change in a setting associated with a first computing environment executing on the computer system, wherein the first change is associated with at least one of an input/output (I/O) device setting, a regional setting, a network setting, a power setting, and a display setting. Next, the system propagates the first change to one or more other computing environments executing on the computer system.

Abstract: A system includes a plurality of cores. Each core includes a processing unit, an on-chip memory (OCM), and an idle detector unit. Data is received and stored in the OCM. Instructions are received to process data in the OCM. The core enters an idle mode if the idle detector unit detects that the core has been idle for a first number of clocking signals. The core receives a command to process when in idle mode and transitions from the idle mode to an operational mode. A number of no operation (No-Op) commands is inserted for each time segment. A No-Op command prevents the core from processing instructions for a certain number of clocking signals. A number of No-Op commands inserted for a first time segment is greater than a number of No-Op commands inserted for a last time segment. After the last time segment no No-Op command is inserted.

Abstract: An information processing device shifts to first and second power states and includes an output unit to output an operation stop signal, and a device to receive the operation stop signal and to shift to an operation stop state based on the operation stop signal, and to shift to an electric power saving mode where less power is consumed than in the operation stop state on condition that the operation stop signal has not been input. A signal control unit provides control that prevents the operation stop signal from being input to the device when the information processing device shifts to the second power state. The signal control unit controls the operation stop signal when a restart unit restarts the information processing device.

Abstract: An image forming apparatus includes a display unit with a power saving function, where the display unit is turned off after a predetermined period of time has elapsed to save power. If however, the display unit is displaying a code used by external devices to establish communication with the image forming apparatus, the power saving function is disabled during the time period the code is being displayed.

Abstract: An exemplary computing environment having a DNN module can maintain one or more bandwidth throttling mechanisms. Illustratively, a first throttling mechanism can specify the number of cycles to wait between transactions on a cooperating fabric component (e.g., data bus). Illustratively, a second throttling mechanism can be a transaction count limiter that operatively sets a threshold of a number of transactions to be processed during a given transaction sequence and limits the number of transactions such as multiple transactions in flight to not exceed the set threshold. In an illustrative operation, in executing these two exemplary calculated throttling parameters, the average bandwidth usage and the peak bandwidth usage can be limited. Operatively, with this fabric bandwidth control, the processing units of the DNN are optimized to process data across each transaction cycle resulting in enhanced processing and lower power consumption.

Abstract: According to examples, an apparatus may include instructions that may cause the processor to identify, for a first device state, a first set of active components of a device and to determine a first power demand level of the first set of active components for the first device state. The instructions may also cause the processor to determine that the device is to transition from the first device state to a second device state, to determine, for the second device state, a second set of active components of the device having a second power demand level that is within a predefined difference level of the first power demand level, the predefined difference level to smooth power delivery to the device between the first device state and the second device state, and to control application of power to the second set of active components during the second device state.