Patents Examined by Stephanie P Duclair
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Patent number: 10424484Abstract: Method for manufacturing a bonded SOI wafer by bonding a bond wafer and base wafer, each composed of a silicon single crystal, via an insulator film, including the steps: depositing a polycrystalline silicon layer on the base wafer bonding surface side, polishing the polycrystalline silicon layer surface, forming the insulator film on the bonding surface of the bond wafer, bonding the polished surface of the base wafer polycrystalline silicon layer and bond wafer via the insulator film; thinning the bonded bond wafer to form an SOI layer; wherein, in the step of depositing the polycrystalline silicon layer, a wafer having a chemically etched surface as base wafer; chemically etched surface is subjected to primary polishing followed by depositing the polycrystalline silicon layer on surface subjected to the primary polishing, and in the step polishing the polycrystalline silicon layer surface, which is subjected to secondary polishing or secondary and finish polishing.Type: GrantFiled: January 7, 2016Date of Patent: September 24, 2019Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Toru Ishizuka, Norihiro Kobayashi, Masatake Nakano
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Patent number: 10421890Abstract: Composite particles with lower mean particle size and smaller size distribution are obtained through refining treatments. The refined composite particles, such as ceria coated silica particles are used in Chemical Mechanical Planarization (CMP) compositions to offer higher removal rate; very low within wafer (WWNU) for removal rate, low dishing and low defects for polishing oxide films.Type: GrantFiled: March 17, 2017Date of Patent: September 24, 2019Assignee: VERSUM MATERIALS US, LLCInventors: Hongjun Zhou, John Edward Quincy Hughes, Krishna P. Murella, Reinaldo Mario Machado, Mark Leonard O'Neill, Dnyanesh Chandrakant Tamboli
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Patent number: 10392297Abstract: A method for manufacturing a substrate is disclosed. The method comprises the following steps: step one, depositing an amorphous silicon layer on a base material; step two, depositing a silicon dioxide layer with a first thickness on the amorphous silicon layer; and step three, etching the silicon dioxide layer until a thickness thereof is reduced to a second thickness. According to the method of the present disclosure, the silicon dioxide layer with a needed thickness can be manufactured on the amorphous silicon layer. When the ELA procedure is performed, the silicon dioxide layer has an enough thickness to prevent the formation of protrusions at grain boundary of polysilicon, so that the semi-conductive layer manufactured therein can have a relatively low roughness.Type: GrantFiled: October 8, 2015Date of Patent: August 27, 2019Assignees: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO. LTD., WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO. LTD.Inventor: Zijian Li
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Patent number: 10385236Abstract: A chemical mechanical polishing (CMP) composition (Q) for chemical mechanical polishing of a substrate (S) containing (i) cobalt and/or (ii) a cobalt alloy, wherein the CMP composition (Q) contains: (A) Inorganic particles, (B) a substituted aromatic compound with at least one carboxylic acid function as corrosion inhibitor, (C) at least one amino acid, (D) at least one oxidizer, (E) an aqueous medium, wherein the CMP composition (Q) has a pH of from 7 to 10.Type: GrantFiled: December 22, 2015Date of Patent: August 20, 2019Assignee: BASF SEInventors: Robert Reichardt, Max Siebert, Yongqing Lan, Michael Lauter, Sheik Ansar Usman Ibrahim, Reza Golzarian, Haci Osman Guevenc, Julian Proelss, Leonardus Leunissen
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Patent number: 10377921Abstract: A process for chemical mechanical polishing a substrate containing cobalt and TiN to planarize the surface and at least improve surface topography of the substrate. The process includes providing a substrate containing cobalt and TiN; providing a polishing composition, containing, as initial components: water; an oxidizing agent; aspartic acid or salts thereof; and, colloidal silica abrasives with diameters of ?25 nm; and, providing a chemical mechanical polishing pad, having a polishing surface; creating dynamic contact at an interface between the polishing pad and the substrate; and dispensing the polishing composition onto the polishing surface at or near the interface between the polishing pad and the substrate; wherein some of the cobalt is polished away to planarize the substrate to provide improved cobalt:TiN removal rate selectivity.Type: GrantFiled: September 21, 2017Date of Patent: August 13, 2019Assignee: Rohm and Haas Electronics Materials CMP Holdings, Inc.Inventors: Murali G. Theivanayagam, Hongyu Wang, Matthew Van Hanehem
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Patent number: 10381231Abstract: Pattern-multiplication via a multiple step ion beam etching process utilizing multiple etching steps. The ion beam is stationary, unidirectional or non-rotational in relation to the surface being etched during the etching steps, but sequential etching steps can utilize an opposite etching direction. Masking elements are used to create additional masking elements, resulting in decreased spacing between adjacent structures and increased structure density.Type: GrantFiled: May 15, 2017Date of Patent: August 13, 2019Assignee: Veeco Instruments Inc.Inventors: Timothy Pratt, Katrina Rook
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Patent number: 10373828Abstract: According to one embodiment, a substrate processing method includes providing a substrate containing Si raised features, depositing a conformal film on the Si raised features, and performing a spacer etch process that removes horizontal portions of the conformal film while substantially leaving vertical portions of the conformal film to form sidewall spacers on the Si raised features, the performing including a) exposing the substrate to a plasma-excited first process gas consisting of H2 gas and optionally an inert gas, and b) exposing the substrate to a plasma-excited second process gas containing i) NF3, O2, H2, and Ar, ii) NF3, O2, and H2, iii) NF3 and O2, iv) NF3, O2, and Ar, v) NF3 and H2, or vi) NF3, H2, and Ar. The method further includes removing the Si raised features while maintaining the sidewall spacers on the substrate. The removing may be performed using steps a) and b).Type: GrantFiled: May 26, 2017Date of Patent: August 6, 2019Assignee: Tokyo Electron LimitedInventors: Alok Ranjan, Sonam D. Sherpa
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Patent number: 10367007Abstract: A display device capable of reducing the number of manufacturing processes and manufacturing costs and a method of manufacturing the display device are provided, the display device including: a first substrate; a gate transmission member and a pixel electrode on the first substrate; a gate insulating layer on the gate transmission member and the pixel electrode; a semiconductor layer on the gate insulating layer, the semiconductor layer overlapping a gate electrode of the gate transmission member; and a source electrode and a drain electrode on the semiconductor layer, wherein the gate transmission member includes a first conductive layer pattern and a second conductive layer pattern on the first conductive layer pattern, the first conductive layer pattern including a material the same as a material forming the pixel electrode.Type: GrantFiled: July 8, 2016Date of Patent: July 30, 2019Assignee: Samsung Display Co., Ltd.Inventor: Youngmin Moon
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Patent number: 10366899Abstract: A method is for detecting a condition associated with a final phase of a plasma dicing process. The method includes providing a non-metallic substrate having a plurality of dicing lanes defined thereon, plasma etching through the substrate along the dicing lanes, wherein during the plasma etching infrared emission emanating from at least a portion of the dicing lanes is monitored so that an increase in infrared emission from the dicing lanes is observed as the final phase of the plasma dicing operation is entered, and detecting the condition associated with the final phase of the plasma dicing from the monitored infrared emission.Type: GrantFiled: June 19, 2017Date of Patent: July 30, 2019Assignee: SPTS Technologies LimitedInventors: Oliver J Ansell, David A Tossell, Gautham Ragunathan
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Patent number: 10358579Abstract: Chemical mechanical polishing (CMP) compositions and methods for planarizing a nickel phosphorus (NiP) substrate are described. A NiP CMP method comprises abrading a surface of the substrate with a CMP composition. The CMP composition comprises a colloidal silica abrasive suspended in an aqueous carrier having a pH of less than 2, and containing a primary oxidizing agent comprising hydrogen peroxide, a secondary oxidizing agent comprising a metal ion capable of reversible oxidation and reduction in the presence of NiP and hydrogen peroxide, a chelating agent, and glycine. The chelating agent comprises two or three carboxylic acid substituents capable of chelating to the metal ion of the secondary oxidizing agent.Type: GrantFiled: December 3, 2013Date of Patent: July 23, 2019Assignee: Cabot Microelectronics CorporationInventors: Ke Zhang, Michael White, Tsung-Ho Lee, Steven Grumbine, Hon-Wu Lau
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Patent number: 10354880Abstract: Embodiments herein describe techniques for forming sidewalls on vertical structures on a semiconductor substrate. In one embodiment, the semiconductor substrate includes a first layer (e.g., a conductive layer such as an electrode) on which a second layer (e.g., an insulator) is disposed. An undercut etch is performed which selectively etches the sides of the material in the first layer but not the material in the second layer. A conformal deposition process is used to deposit the material of the sidewall into the undercut regions. Further etches can be performed to shape the sidewalls disposed on the sides of the material in the first layer.Type: GrantFiled: April 5, 2017Date of Patent: July 16, 2019Assignee: International Business Machines CorporationInventors: Joel P. De Souza, Yun Seog Lee, Devendra K. Sadana
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Patent number: 10336609Abstract: First, an ion beam is applied to a workpiece to form a tapered hole the side wall of which is inclined. Next, the application of the ion beam is stopped, and then a material gas is introduced from the gas source to the upper surface of the workpiece from an oblique direction to cause gas molecules to be adsorbed to the upper surface of the workpiece and to the upper portion of the side wall of the hole. Next, introduction of the material gas is stopped, and then the ion beam is applied again to the region of the workpiece where the hole is formed. As a result, at the upper portion of the side wall of the hole, film formation occurs using the gas molecules as the material adsorbed to the side wall of the hole, and, at the bottom portion of the hole, etching of the workpiece occurs.Type: GrantFiled: June 1, 2017Date of Patent: July 2, 2019Assignee: Hitachi, Ltd.Inventors: Keiji Watanabe, Shuntaro Machida, Katsuya Miura, Aki Takei, Tetsufumi Kawamura, Nobuyuki Sugii, Daisuke Ryuzaki
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Patent number: 10336023Abstract: The invention relates in particular to a method for creating patterns in a layer (410) to be etched, starting from a stack comprising at least the layer (410) to be etched and a masking, layer (420) on top of the layer (410) to be etched, the masking layer (420) having at least one pattern (421), the method comprising at least: a) a step of modifying at least one zone (411) of the layer (410) to be etched via ion implantation (430) vertically in line with said at least one pattern (421); b) at least one sequence of steps comprising: b1) a step of enlarging (440) the at least one pattern (421) in a plane in which the layer (410) to be etched mainly extends; b2) a step of modifying at least one zone (411?, 411?) of the layer (410) to be etched via ion implantation (430) vertically in line with the at least one enlarged pattern (421), the implantation being carried out over a depth less than the implantation depth of the preceding, modification step; c) a step of removing (461, 462) the modified zones (411Type: GrantFiled: December 22, 2015Date of Patent: July 2, 2019Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Nicolas Posseme, Stefan Landis, Lamia Nouri
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Patent number: 10332744Abstract: Techniques herein include forming single or multi-layer mandrels and then forming one or more lines of material running along sidewalls of the mandrels. A relatively thin portion of mandrel material stretches from a base of mandrels to each other and underneath sidewall spacers and other fill materials, thereby forming a film of mandrel material over an underlying layer, which provides advantages with etch selectivity in a patterning process. Accordingly a multi-line layer is formed with materials having different etch resistivities to be able to selectively etch one or more of the materials to create features where specified. Etching using an etch mask positioned above or below this multi-line layer further defines a pattern that is transferred into an underlying layer.Type: GrantFiled: April 28, 2017Date of Patent: June 25, 2019Assignee: Tokyo Electron LimitedInventors: Anton J. deVilliers, Andrew W. Metz
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Patent number: 10319599Abstract: A method of planarizing a roughened surface of a SiC substrate includes: forming a sacrificial material on the roughened surface of the SiC substrate, the sacrificial material having a density between 35% and 120% of the density of the SiC substrate; implanting ions through the sacrificial material and into the roughened surface of the SiC substrate to form an amorphous region in the SiC substrate; and removing the sacrificial material and the amorphous region of the SiC substrate by wet etching.Type: GrantFiled: May 31, 2017Date of Patent: June 11, 2019Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Helmut Oefner, Roland Rupp
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Patent number: 10312106Abstract: A method of manufacturing a semiconductor device includes exposing a material to a semi-aqueous etching solution. The semi-aqueous etching solution comprises a solvent which chelates with the material and acts as a catalyst between the etching driving force and the material. As such, the etching driving force may be used to remove the material.Type: GrantFiled: November 1, 2017Date of Patent: June 4, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yao-Wen Hsu, Jian-Jou Lian, Neng-Jye Yang, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang, Li-Min Chen
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Patent number: 10297461Abstract: The present invention provides a CMP polishing agent containing polishing particles, a protective agent, and water, wherein the protective agent is a silsesquioxane polymer having a polar group. This provides a CMP polishing agent which can reduce polishing scratches produced due to polishing in a CMP process and has high polishing selectivity.Type: GrantFiled: August 28, 2015Date of Patent: May 21, 2019Assignee: SHIN-ETSU CHEMICAL CO., LTD.Inventor: Mitsuhito Takahashi
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Patent number: 10290506Abstract: A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm).Type: GrantFiled: February 13, 2017Date of Patent: May 14, 2019Assignee: Tokyo Electron LimitedInventors: Alok Ranjan, Akiteru Ko
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Patent number: 10290510Abstract: A plasma etching method is performed by forming a desired pattern of a mask into a film including a zirconium oxide film by plasma etching with plasma generated from a first gas. The first gas consists of at least one chloride-containing gas of the group of boron trichloride, tetrachloromethane, chloride and silicon tetrachloride, at least one hydrogen-containing gas of the group of hydrogen bromide, hydrogen and methane, and a noble gas. An underlying film of a silicon oxide film or an amorphous carbon film is provided underneath the zirconium oxide film, and an etching selectivity of the zirconium oxide film to the underlying film is greater than or equal to one.Type: GrantFiled: April 5, 2016Date of Patent: May 14, 2019Assignee: Tokyo Electron LimitedInventor: Shunichi Mikami
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Patent number: 10265699Abstract: A fluid sampler includes: a sample cell that includes: a substrate comprising: a first port; a second port in fluid communication with the first port; a viewing reservoir in fluid communication with the first port and the second port and that receives the fluid from the first port and communicates the fluid to the second port, the viewing reservoir including: a first view membrane; a second view membrane; and a pillar interposed between the first view membrane and second view membrane, the pillar separating the first view membrane from the second view membrane at a substantially constant separation distance such that a volume of the viewing reservoir is substantially constant and invariable with respect to a temperature and invariable with respect to a pressure to which the sample cell is subjected.Type: GrantFiled: June 1, 2017Date of Patent: April 23, 2019Assignee: THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCEInventors: J. Alexander Liddle, Samuel M. Stavis, Glenn E. Holland