Patents Examined by Stephanie P Duclair
  • Patent number: 10991809
    Abstract: A removal composition and process for selectively removing p-doped polysilicon (e.g., boron-doped polysilicon) relative to silicon nitride from a microelectronic device having said material thereon. The substrate preferably comprises a high-k/metal gate integration scheme.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: April 27, 2021
    Assignee: ENTEGRIS, INC.
    Inventors: Steven Bilodeau, Emanuel I Cooper
  • Patent number: 10982114
    Abstract: A composition including a carrier comprising a liquid, an abrasive particulate contained in the carrier, an accelerant contained in the carrier, the accelerant including at least one free anion selected from the group of iodide (I?), bromide (Br?), fluoride (F?), sulfate (SO42?), sulfide (S2?), sulfite (SO32?), chloride (Cl?), silicate (SiO44?), phosphate (PO43?), nitrate (NO3?), carbonate (CO32?), perchlorate (ClO4?), or any combination thereof, and a buffer contained in a saturated concentration in the carrier, the buffer including a compound selected from MaFx, NbFx, MaNbFx, MaIx, NbIx, MaNbIx, MaBrx, NbBrx, MaNbBrx, Ma(SO4)x, Nb(SO4)x, MaNb(SO4)x, MaSx, NbSx, MaNbSx, Ma(SiO4)x, Nb(SiO4)x, MaNb(SiO4)x, Ma(PO4)x, Nb(PO4)x, MaNb(PO4)x, Ma(NO3)x, Nb(NO3)x, MaNb(NO3)x, Ma(CO3)x, Nb(CO3)x, MaNb(CO3)x, or any combination, wherein M represents a metal element or metal compound; N represents a non-metal element; and a, b, and x is 1-6.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: April 20, 2021
    Assignee: SAINT-GOBAIN CERAMICS & PLASTICS, INC.
    Inventors: Ian T. Sines, Stephen Bottiglieri, Douglas E. Ward, Nabil Nahas, Mark Hampden-Smith, Steven L. Robare
  • Patent number: 10985025
    Abstract: Methods for forming semiconductor fins include forming a protective layer around a base of a hardmask fin on an underlying semiconductor layer. A portion of the hardmask fin is etched away with an etch that is selective to the protective layer. A semiconductor fin is etched from the semiconductor layer using the etched hardmask fin as a mask.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: April 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Eric R. Miller, Stuart A. Sieg, Yann Mignot, Indira Seshadri, Christopher J. Waskiewicz
  • Patent number: 10983257
    Abstract: A lithographic patterning of a resist is performed to create a mandrel over a substrate. A deposition of one or more functional materials on the mandrel is performed. And each functional material has a respective refractive index. A selective removal of the mandrel is performed to create a plurality of grating elements formed from the one or more functional materials. The plurality of grating elements are self-aligned and form a diffraction grating. Each grating element may have a heterogenous refractive index (e.g., substantial normal to and/or parallel to a surface of the substrate). The diffraction grating may be used in a near-eye display.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: April 20, 2021
    Assignee: Facebook Technologies, LLC
    Inventors: Matthew E. Colburn, Giuseppe Calafiore, Matthieu Charles Raoul Leibovici, Maxwell Parsons
  • Patent number: 10978300
    Abstract: Embodiments are disclosed that reduce gouging during multi-patterning processes using thermal decomposition materials. For one embodiment, gouging is reduced or suppressed by using thermal decomposition materials as cores during multiple patterning processes. For one embodiment, gouging is reduced or suppressed by using thermal decomposition materials as a gap fill material during multiple patterning processes. By using thermal decomposition material, gouging of an underlying layer, such as a hard mask layer, can be reduced or suppressed for patterned structures being formed using the self-aligned multi-patterning processes because more destructive etch processes, such as plasma etch processes, are not required to remove the thermal decomposition materials.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: April 13, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yuki Kikuchi, Toshiharu Wada, Kaoru Maekawa, Akiteru Ko
  • Patent number: 10968366
    Abstract: A chemical mechanical polishing composition for polishing a substrate includes a liquid carrier and cationic metal oxide abrasive particles dispersed in the liquid carrier. The cationic metal oxide abrasive particles have a surface modified with at least one compound consisting of a silyl group having at least one quaternary ammonium group. A method for chemical mechanical polishing a substrate including a metal layer includes contacting the substrate with the above described polishing composition, moving the polishing composition relative to the substrate, and abrading the substrate to remove a portion of the metal layer from the substrate and thereby polish the substrate.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: April 6, 2021
    Assignee: CMC Materials, Inc.
    Inventors: Steven Kraft, Fernando Hung Low, Daniel Clingerman, Roman A. Ivanov, Steven Grumbine
  • Patent number: 10961414
    Abstract: A polishing slurry including a composite including a hydrophilic fullerene and an ionic compound, a method of manufacturing the same, and a method of manufacturing a semiconductor device.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: March 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kenji Takai, Sang Eui Lee, Ken Kokubo, Eigo Miyazaki, Do Yoon Kim
  • Patent number: 10950430
    Abstract: Embodiments of the present disclosure relate to methods for in-situ deposition and treatment of a thin film for improved step coverage. In one embodiment, the method for processing a substrate is provided. The method includes forming a dielectric layer on patterned features of the substrate by exposing the substrate to a gas mixture of a first precursor and a second precursor simultaneously with plasma present in a process chamber, wherein the plasma is formed by a first pulsed RF power, exposing the dielectric layer to a first plasma treatment using a gas mixture of nitrogen and helium in the process chamber, and performing a plasma etch process by exposing the dielectric layer to a plasma formed from a gas mixture of a fluorine-containing precursor and a carrier gas, wherein the plasma is formed in the process chamber by a second pulsed RF power.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: March 16, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Vinayak Veer Vats, Hang Yu, Deenesh Padhi, Changling Li, Gregory M. Amico, Sanjay G. Kamath
  • Patent number: 10942296
    Abstract: The present invention provides a processing method of a cover plate, a control apparatus, a cover plate processing apparatus, and a storage medium. The processing method utilizes a scanning device to scan surfaces and obtain surface features of a first cover plate and a second cover plate, and performs Fourier transformation on the surface features of the first cover plate and the second cover plate to obtain the surface feature frequency variation distribution curves of the first cover plate and the second cover plate, thereby to obtain the surface feature frequency variation distribution curves of a high-resolution cover plate. Fourier inverse transformation is performed on the surface feature frequency variation distribution curves of the high-resolution cover plate to obtain surface features of a target cover plate, so that the high-resolution cover plate so processed meets balancing speckles and anti-glare requirements.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: March 9, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yong Yang
  • Patent number: 10934457
    Abstract: Slurry compositions useable in chemical mechanical polishing processes, as well as methods of making and methods of using the same, are described.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: March 2, 2021
    Assignee: The University of Toledo
    Inventors: Matthew Liberatore, Ehsan Akbari Fakhrabadi
  • Patent number: 10930504
    Abstract: Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: February 23, 2021
    Assignee: Tessera, Inc.
    Inventors: John Christopher Arnold, Sean D. Burns, Yann Alain Marcel Mignot, Yongan Xu
  • Patent number: 10928725
    Abstract: A method for the directed self-assembly of a block copolymer by graphoepitaxy, includes forming a guide pattern, the guide pattern having a cavity with a bottom and side walls; forming a functionalisation layer on the guide pattern that has a first portion and a second portion disposed, respectively, on the bottom and side walls of the cavity; forming a protective layer on the first and second portions of the functionalisation layer; etching the protective layer and the second portion of the functionalisation layer such that a portion of the protective layer is retained and the side walls of the cavity are exposed, the retained portion of the protective layer having a thickness of less than 15 nm; selectively etching the portion of the protective layer relative to the first portion of the functionalisation layer and to the guide pattern; and depositing a block copolymer in the cavity.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: February 23, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Raluca Tiron, Nicolas Posseme, Xavier Chevalier, Christophe Navarro
  • Patent number: 10920320
    Abstract: Methods of monitoring a plasma while processing a semiconductor substrate are described. In embodiments, the methods include determining the difference in power between the power delivered from the plasma power supply and the power received by the plasma in a substrate processing chamber. The power received may be determined using a V/I sensor positioned after the matching circuit. The power reflected or the power lost is the difference between the delivered power and the received power. The process may be terminated by removing the delivered power if the reflected power is above a setpoint. The VRF may further be fourier transformed into frequency space and compared to the stored fourier transform of a healthy plasma process. Missing frequencies from the VRF fourier transform may independently or further indicate an out-of-tune plasma process and the process may be terminated.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: February 16, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Junghoon Kim, Soonam Park, Tae Seung Cho, Dmitry Lubomirsky, Nikolai Kalnin
  • Patent number: 10916442
    Abstract: Disclosed is a method for etching an etching target layer which contains silicon and is provided with a metal-containing mask thereon. The method includes: generating plasma of a first processing gas containing a fluorocarbon gas in a processing container that accommodates the etching target layer and the mask to form a fluorocarbon-containing deposit on the mask and the etching target layer; and generating plasma of a second processing gas containing an inert gas in the processing container to etch the etching target layer by radicals of the fluorocarbon contained in the deposit. A plurality of sequences, each including the generating the plasma of the first processing gas and the generating the plasma of the second processing gas, are performed.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: February 9, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Takayuki Katsunuma
  • Patent number: 10916437
    Abstract: Provided herein is a method of forming micropatterns, including: forming an etching target film on a substrate; forming a photosensitivity assisting layer on the etching target film, the photosensitivity assisting layer being terminated with a hydrophilic group; forming an adhesive layer on the photosensitivity assisting layer, the adhesive layer forming a covalent bond with the hydrophilic group; forming a hydrophobic photoresist film on the adhesive layer; and patterning the photoresist film.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: February 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Shin Jang, Jong-Min Baek, Hoon-Seok Seo, Eui-Bok Lee, Sung-Jin Kang, Vietha Nguyen, Deok-Young Jung, Sang-Hoon Ahn, Hyeok-Sang Oh, Woo-Kyung You
  • Patent number: 10913240
    Abstract: Disclosed herein is a method of manufacturing an interior material, which can implement various and distinct light emission effects by disposing a light-blocking layer configured to block light emitted from a light source on a wood layer or transparent film and then allowing the component of the transparent film to fill lighting grooves formed by laser-etching. Since a tape configured to support an island is employed, stable manufacturing is possible throughout an overall process.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: February 9, 2021
    Assignees: INTOPS CO., LTD.
    Inventors: Keun ha Kim, Won jae Choi, Hong il Lee
  • Patent number: 10910228
    Abstract: Surface treatment processes for treating a workpiece with organic radicals are provided. In one example implementation, a method for processing a workpiece having a semiconductor material and a carbon containing layer (e.g., photoresist) can include a surface treatment process on the workpiece. The surface treatment process can include generating one or more species in a first chamber (e.g., a plasma chamber). The surface treatment process can include mixing one or more hydrocarbon radicals with the species to create a mixture. The surface treatment process can include exposing the carbon containing layer to the mixture in a second chamber (e.g., a processing chamber).
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: February 2, 2021
    Assignees: Mattson Technolgoy, Inc., Beijing E-Town Semiconductor Technology Co., Ltd.
    Inventors: Michael X. Yang, Hua Chung, Xinliang Lu
  • Patent number: 10898897
    Abstract: Techniques relate to forming a sorting device. A mesh is formed on top of a substrate. Metal assisted chemical etching is performed to remove substrate material of the substrate at locations of the mesh. Pillars are formed in the substrate by removal of the substrate material. The mesh is removed to leave the pillars in a nanopillar array. The pillars in the nanopillar array are designed with a spacing to sort particles of different sizes such that the particles at or above a predetermined dimension are sorted in a first direction and the particles below the predetermined dimension are sorted in a second direction.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: January 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huan Hu, Joshua T. Smith, Gustavo A. Stolovitzky, Benjamin H. Wunsch
  • Patent number: 10894906
    Abstract: Composite particles with lower mean particle size and smaller size distribution are obtained through refining treatments. The refined composite particles, such as ceria coated silica particles are used in Chemical Mechanical Planarization (CMP) compositions to offer higher removal rate; very low within wafer (WWNU) for removal rate, low dishing and low defects for polishing oxide films.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: January 19, 2021
    Assignee: Versum Materials US, LLC
    Inventors: Hongjun Zhou, John Edward Quincy Hughes, Krishna P. Murella, Reinaldo Mario Machado, Mark Leonard O'Neill, Dnyanesh Chandrakant Tamboli
  • Patent number: 10892145
    Abstract: A substrate processing method includes providing a substrate into a process chamber; introducing a reference light into the process chamber; generating a plasma light in the process chamber while performing an etching process on the substrate; receiving the reference light and the plasma light; and detecting an etching end point by analyzing the plasma light and the reference light. Detecting the etching end point includes a compensation adjustment based on a change rate of an absorption signal of the reference light with respect to a change rate of an emission signal of the plasma light.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: January 12, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sejin Oh, Kyohyeok Kim, Jongwoo Sun, Dougyong Sung, Sung-Ki Lee, Jaehyun Lee