Abstract: Provided is a decoding method for detecting Physical Layer Signaling Codes (PLSCs) from frames of a satellite broadcasting system. The method includes: a) acquiring a summation vector and a subtraction vector from an inputted symbol vector; b) performing parallel Reed-Muller (32,6) decoding onto the summation and subtraction vectors based on a Hadamard matrix and estimating message bits of the summation and subtraction vectors; c) performing PLSC coding and modulation onto the message bits of the summation and subtraction vectors; d) calculating a first difference between symbols of the received symbol vector and the summation vector symbols, and a second difference between the symbols of the received symbol vector and the subtraction vector symbols; and e) when the first difference is smaller than the second difference, determining a Reed-Muller codeword is repeated, or when the first difference is larger than the second difference, determining that the Reed-Muller codeword is inverted.

Abstract: A method that employs a piecewise linear algorithm, P, to map m-dimensional symbols into code tuples, followed by the construction of codes of weight m from the code tuples. To reverse the operation, constant weight codes are converted to code tuples, and a reverse piecewise linear algorithm P? is used to map the code tuples into symbols, from which data is recovered. The m-dimensional symbols are obtained from mapping of input data into the symbols, which are contained within an m-dimensional parallelopiped, with each coordinate having a different span but the symbols along each of the coordinate are equally spaced apart. The code tuples, which are obtained by employing process P, are contained within an m-dimensional simplex.

Abstract: Methods, systems, and apparatus are provided to generate a Viterbi path for a DBN. The DBN is converted to a chain of junction trees, where each tree represents a decision-making process. The trees are forwardly iterated and the Viterbi path is generated during the forward iteration (forward pass). This is achieved by maintaining backpointers to previously processed junction trees during the forward pass and dynamically assembling the Viterbi with each pair of junction trees during the forward pass.

Abstract: An ACS circuit and a Viterbi decoder with the circuit. The Add-Compare-Select (ACS) circuit comprises: two registers for storing two previous candidate state metrics; a first adder for adding the value stored in the first register and a first branch metric to generate a first addition result; a second adder for adding the value stored in the second register and the first branch metric to generate a second addition result; a comparator for comparing the values stored in the first register and the second register to generate a decision bit; and a multiplexer for selecting either the first addition result or the second addition result as a new output candidate state metric according to the decision bit. Due to the parallel processing of the adders and the comparator, the processing speed of a Viterbi decoder with the ACS will be increased.

Abstract: Techniques are described for detecting corruption of buffer pointers passed between a local processor and a remote processor on a network device. For example, the first processor, which may be a memory controller, receives and stores packets within memory. A second processor, such as a host processor for the network device, is coupled to the first processor by a bus. The first processor communicates a memory pointer associated with an a given packet to the second processor for processing of the packet, and maintains a backup copy of the memory pointer. Upon receiving the memory pointer back from the second processor, the first processor compares at least a portion of the memory pointer received from the second processor with an equivalent portion of the copy of the memory pointer to determine whether the received memory pointer has been corrupted.

Abstract: The communication method includes the use of CRC codes for additional error correction in addition to the error detection capability. The method is for error detection and correction in a received message that includes N message bits and M Cyclic Redundancy Check (CRC) bits appended thereto. It is determined whether at least one bit error has occurred in the N message bits and M CRC bits of the received message based upon the M CRC bits, and when at least one bit error is determined, then K bits with a lowest quality metric are selected from the N message bits and M CRC bits. The bit error is corrected based upon possible bit error patterns and the selected K bits. Multiple bit errors may also be corrected.

Abstract: The present invention relates to an improved decoding scheme for use in a concatenated channel decoder. In the present invention, the decoding of the concatenated code is done iteratively to increase the confidence for any corrected symbols. As a result, the overall performance of the decoder is improved. This iterative process comprises using a Maximal a posteriori (MAP) decoder which generates decoded information, to include Erasure Information. The output of the MAP decoder is then supplied to a Reed Solomon (RS) decoder, which attains better error correction performance by using this Erasure Information. This improved output of the RS decoder is then supplied back to the MAP decoder, thereby improving the performance of the system.

Abstract: Circuit arrangement for secure data processing for program data with a protected data record. An internal memory provides a protected data record having instruction words and a first check word associated with the instruction words. An arithmetic and logic unit has an input coupled to the internal memory and outputs the first check word from the applied protected data record. A checking apparatus has an input coupled between the internal memory and the arithmetic and logic unit, and allocates a second check word to the instruction words in the protected data record. A comparison apparatus has respective inputs coupled to the checking apparatus and the arithmetic and logic unit, and compares the first check word with the second check word, and outputs an alarm signal when the first check word does not match the second check word.

Abstract: Circuits, architectures, methods and algorithms for joint channel-code decoding of linear block codes, and more particularly, for identifying and correcting one or more errors in a code word and/or for encoding CRC (or parity) information. In one aspect, the invention focuses on use of (i) remainders, syndromes or other polynomials and (ii) Gaussian elimination to determine and correct errors. Although this approach may be suboptimal, the present error checking and/or detection scheme involves simpler computations and/or manipulations than conventional schemes, and is generally easier to implement logically.

Abstract: A method of validating a bitstream loaded into a circuit having a programmable circuit is disclosed. According to one embodiment, the method comprises steps of loading a configuration bitstream comprising an error detection command at an input of the circuit; decoding the bitstream; providing a signal indicating that an error detection should be performed to a state machine when an error detection command has been decoded; and restarting the loading of the configuration bitstream if the signal has not been received. A device having a programmable circuit is also disclosed.

Abstract: A cyclic redundancy check (CRC) system for a storage controller comprises a memory that stores first sector data and a corresponding CRC non-zero seed value. A buffer control module includes a CRC module, calculates a CRC value of the first sector data with the CRC module, and combines the CRC value with the CRC non-zero seed value.

Abstract: In an exclusive OR circuit (XOR gate) constituting an ECC circuit, the drivability of P channel MOS transistors is set larger than the drivability of N channel MOS transistors. Accordingly, the speed of the logic level of an output node being set to an H level from an L level identified as a reset state is increased than the case where the drivability is set equal. Thus, the time required to output a syndrome from a plurality of stages of XOR gates can be reduced to allow execution of error correction processing at high speed.

Abstract: A method and an apparatus for encoding and decoding a modulation code are provided. The method includes: adding an error detection bit(s) to source information; performing k-constraint coding by inserting an error pattern that can be detected using an error detection code into a data stream that violates a k-constraint for a run length limited (RLL) code in a data stream comprising the error detection bit(s) and the source information, and recording the data stream after being k-constraint coded onto a recording medium; and reading the data stream recorded onto the recording medium and determining whether an error is present in the data stream.

Abstract: A compact high-speed data encoder/decoder for single-bit forward error-correction, and methods for same. This is especially useful in situations where hardware and software complexity is restricted, such as in a monolithic flash memory controller during initial startup and software loading, where robust hardware and software error correction is not feasible, and where rapid decoding is important. The present invention arranges the data to be protected into a rectangular array and determines the location of a single bit error in terms of row and column positions. So doing greatly reduces the size of lookup tables for converting error syndromes to error locations, and allows fast error correction by a simple circuit with minimal hardware allocation. Use of square arrays reduces the hardware requirements even further.

Abstract: A decoder suitable for use in a digital communications system utilizing an RS(n?, k?) code modified from an RS(n, k) code receives n?-symbol vectors each including k? message symbols and r?=n??k? parity symbols and decodes the n?-symbol vectors to correct errors therein, wherein n, k, n?, and k? are integers, and k?<n?<n, k?<k<n, and wherein the decoder stores therein one erasure locator polynomial ?0(x). The decoder includes a syndrome calculator for receiving the n?-symbol vectors and for calculating syndromes of each n?-symbol vector, wherein the i-th syndrome Si of one n?-symbol vector R?, (rn??1, rn??2, . . . , r0), is Si=Rs(?i+1) for i=0, 1, . . . , n?k?1, wherein Rs(x)=rn??1xn??1+rn??2xn??2+ . . . +r0, and means for finding the locations and values of the errors in each n?-symbol vector using the syndromes thereof and the one erasure locator polynomial ?0(x).

Abstract: A congestion/non-congestion determining unit determines whether or not a communications network is in a congestion state. An FEC (forward error correction) packet generator generates error correction packets containing error correction data for correcting error of streaming data contained in transmission packets. When the determination result changes from a non-congestion state to a congestion state, an FEC transmission controller controls the error-correction-packet generation so as to change the number of error correction packets. The present invention is applicable to a remote TV conference system.

Abstract: A reconfigurable decoder is capable of performing both Viterbi decoding and turbo decoding. The reconfigurable decoder may be repeatedly reconfigured to work with any of a number of different convolutional or turbo coding schemes. In at least one embodiment, the reconfigurable decoder is capable of automatically reconfiguring itself based on a present signal environment about a communication device carrying the decoder.

Abstract: The present invention provides a decoding apparatus for carrying out a decoding process on a ring-R linear code. The decoding apparatus includes coded-word holding means for acquiring a coded word with a code length reduced by omission of some symbols from the coded word and for holding the coded word; known-information addition means for attaching a reliability level of each of the symbols omitted from the coded word to reduce its code length as known symbols each having a known value to the coded word held by the coded-word holding means as known information; and repetitive decoding means for repeatedly carrying out a decoding process using belief propagation on the coded word including the known information attached to the coded word by the known-information addition means.

Abstract: A low density parity check (LDPC) code generating method and apparatus are provided. A parity check matrix with (N?K) rows for check nodes and N columns for variable nodes are formed to encode an information sequence of length K to a codeword of length N. The parity check matrix is divided into an information part matrix with K columns and a parity part matrix with (N?k) columns. The parity part is divided into P×P subblocks. P is a divisor of (N?K). First and second diagonals are defined in the parity part matrix and the second diagonal is a shift of the first diagonal by f subblocks. Shifted identity matrices are placed on the first and second diagonals and zero matrices are filled elsewhere. An odd number of delta matrices each having only one element of 1 are placed in one subblock column of the parity part matrix. The parity check matrix is stored.

Abstract: A method and apparatus for Turbo encoding uses a set of rate-compatible Turbo Codes optimized at high code rates and derived from a universal constituent code. The Turbo Codes have rate-compatible puncturing patterns. The method comprises: encoding a signal at a first and second encoder using a best rate 1/2 constituent code universal with higher code rates, the first encoder and the second encoder each producing a respective plurality of parity bits for each information bit; puncturing the respective plurality of parity bits at each encoder with a higher rate best puncturing patterns; and puncturing the respective plurality of parity bits at each encoder with a lower rate best puncturing pattern. In a variation, the best rate 1/2 constituent code represents a concatenation of polynomials 1+D2+D3 (octal 13) and 1+D+D3 (octal 15), D a data bit. A Turbo Encoder is provided which has hardware to implement the method.