Abstract: Devices and methods are provided to construct resistive random-access (RRAM) array structures which comprise RRAM memory cells, wherein each RRAM memory cell is formed of multiple parallel-connected RRAM devices to reduce the effects of resistive switching variability of the RRAM memory cells.

Abstract: A first and a second instance of a common structured stack are formed, respectively, on a first fin and a second fin. The common structured stack includes a work-function metal layer, and a barrier layer. The barrier layer of the first instance of the common structured stack is etched through, and the work-function metal layer of the first instance of the common structure is partially etched. The partial etch forms a thinner work-function metal layer, having an oxide of the work-function metal as a new barrier layer. A gate element is formed on the new barrier layer.

Abstract: In a general aspect, a power semiconductor device can include a silicon carbide (SiC) substrate and a SiC epitaxial layer disposed on the SiC substrate. The device can include a well region disposed in the epitaxial layer, a source region disposed in the well region and a gate trench disposed in the epitaxial layer and adjacent to the source region. The gate trench can have a depth that is greater than a depth of the well region and less than a depth of the epitaxial layer. The device can include a hybrid gate dielectric disposed on a sidewall of the gate trench and a bottom surface of the gate trench. The hybrid gate dielectric can include a first high-k material and a second high-k dielectric material that is different than the first high-k dielectric material. The device can include a conductive gate electrode disposed on the hybrid gate dielectric.

Abstract: Disclosed are an organic light emitting display device to improve optical efficiency and prevent deterioration in reliability of thin film transistors, and a method of manufacturing the same. The organic light emitting display device includes a mirror wall which is disposed on a substrate such that the mirror wall surrounds a light emitting area of each sub-pixel where a light emitting element is disposed, thus preventing total reflection of light produced in the light emitting element and improving optical efficiency by reflecting light travelling toward a non-emitting area to be directed to the light emitting area.

Abstract: A display device is disclosed. In one aspect, the display device includes a substrate including a display area, the display area including a plurality of pixels configured to display an image and a pad area adjacent to the pad area and configured to transfer electrical signals. At least a portion of the pad area is bendable. The display device also includes an insulating layer formed over the substrate and including a bending groove in the pad area. The bending groove includes a sidewall. A plurality of peripheral wires is formed over the insulating layer, and a cutoff portion is connected to the sidewall and disposed between adjacent peripheral wires.

Abstract: A semiconductor module is provided with a conductive member having one end, in a longitudinal direction, joined to an electrode of a semiconductor element that is mounted on an insulating substrate, the other end of the conductive member in the longitudinal direction being joined to a component different from the electrode. The conductive member is made up of a metal sheet, and has a bent portion at the one end and at the other end. The bent portion provided at the one end has a cut in a leading end portion, in the longitudinal direction, and an end joining section at which the cut is not present is joined to the electrode of the semiconductor element. As a result, a semiconductor module can be realized that allows combination of increased current capacity with improved reliability.

Abstract: A method for manufacturing at least one light emitting diode (LED) includes epitaxying at least one light emitting diode (LED) structure on a growth substrate; forming at least one supporting layer on the LED structure; temporarily adhering the supporting layer to a carrier substrate through an adhesive layer, in which the supporting layer has a Young's modulus greater than that of the adhesive layer; and removing the growth substrate from the LED structure.

Abstract: A method of processing a workpiece is disclosed, where the interior surfaces of the plasma chamber are first coated using a conditioning gas that contains the desired dopant species. A working gas, which does not contain the desired dopant species, is then introduced and energized to form a plasma. This plasma is used to sputter the desired dopant species from the interior surfaces. This dopant species is deposited on the workpiece. A subsequent implant process may then be performed to implant the dopant into the workpiece. The implant process may include a thermal treatment, a knock in mechanism, or both.

Abstract: In a method for fabricating a field-effect transistor (FET) structure, forming a fin on a semiconductor substrate. The method further includes forming a gate on a portion of the fin and the semiconductor substrate. The method further includes epitaxially growing a semiconductor material on the fin. The method further includes depositing oxide covering the fin and the epitaxially grown semiconductor material. The method further includes recessing the deposited oxide and the epitaxially grown semiconductor material to expose a top portion of the fin. The method further includes removing the fin. In another embodiment, the method further includes epitaxially growing another fin in a respective trench formed by removing the first set of fins.

Abstract: An integrated optical sensor comprises a semiconductor substrate (1), an integrated circuit (2), a dielectric layer (6), a wiring (4), a structured filter layer (7) and a diffuser (10). The semiconductor substrate (1) has a main surface (11) and the integrated circuit (2) is arranged in the substrate (1) at or near the main surface (11). Furthermore, the integrated circuit (2) comprises at least one light sensitive component (3). The dielectric layer (6) comprises at least one compound of the semiconductor material. The dielectric layer (6) is arranged on or above the main surface (11). The wiring (4) is arranged in the dielectric layer (6) and provides an electrical connection to the integrated circuit (2), i.e. the wiring is connected to the integrated circuit (2). The structured filter layer (7) is arranged on the dielectric layer (6) and faces the at least one light sensitive component (3), i.e. the diffusor (10) is positioned over the structured filter layer (7).

Abstract: Light emitter packages, systems, and methods having improved performance are disclosed. In one aspect, a light emitter package can include a submount that can include an anode and a cathode. A light emitter chip can be disposed over the submount such that the light emitter chip is mounted over at least a portion of the cathode and wirebonded to at least a portion of the anode.

Abstract: A method is presented for forming a transistor having reduced parasitic contact resistance. The method includes forming a first device over a semiconductor structure, forming a second device adjacent the first device, forming an ILD over the first and second devices, and forming recesses within the ILD to expose the source/drain regions of the first device and the source/drain regions of the second device. The method further includes forming a first dielectric layer over the ILD and the top surfaces of the source/drain regions of the first and second devices, a chemical interaction between the first dielectric layer and the source/drain regions of the second device resulting in second dielectric layers formed over the source/drain regions of the second device, and forming an epitaxial layer over the source/drain regions of the first device after removing remaining portions of the first dielectric layer.

Abstract: A magnetic memory device is provided including a magnetic tunnel junction pattern having a free pattern, a reference pattern, and a tunnel barrier pattern between the free pattern and the reference pattern. The free pattern includes a first sub-free pattern, a second sub-free pattern, and a third sub-free pattern. The first sub-free pattern is between the tunnel barrier pattern and the third sub-free pattern, and the second sub-free pattern is between the first sub-free pattern and the third sub-free pattern. The second sub-free pattern includes nickel-cobalt-iron-boron (NiCoFeB), and the third sub-free pattern includes nickel-iron-boron (NiFeB). Related methods of fabrication are also provided.

Abstract: A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a pattern to elongate the fin and form a second portion of the fin in the substrate, the second portion having a width that is greater than the first portion; oxidizing a region of the second portion of the fin beneath the spacer material to form an oxidized channel region; and removing the oxidized channel region to form a vacuum channel.

Abstract: A semiconductor light emitting element includes a first semiconductor layer, an active layer, a second semiconductor layer, a first conducting layer, a second conducting layer, and an insulating layer. The insulating layer is disposed at least on or above the upper surface of the second conducting layer. Holes are opened at given intervals through the second semiconductor layer to expose the first semiconductor layer at bottom surfaces of the holes. In each of the holes, the insulating layer covers from a side-wall surface of each of the holes to a first region provided on or above the upper surface of the second conducting layer around a top of each of the holes. The first conducting layer covers from the bottom surface of each of the holes to a second region provided over the second conducting layer and the insulating layer around the top of each of the holes.

Abstract: A semiconductor module is disclosed. The semiconductor module includes a housing that encloses on a bottom thereof a spacer and a wiring substrate that mounts a semiconductor element thereon. The housing includes a feedthrough that secures one end of a transmission substrate. The other end of the transmission substrate faces the wiring substrate and the spacer. The other end of the transmission substrate provides a lower end and an upper end that form an extension protruding toward the wiring substrate. The upper end is set so close to the wiring substrate but the lower end forms a space for receiving a surplus adhesive oozing between the spacer and the wiring substrate.

Abstract: A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and a plurality of wirings and a solder resist layer that are provided on a front surface of the substrate body. The plurality of solder-including electrodes include a plurality of first electrodes and a plurality of second electrodes. The plurality of first electrodes supply a first electric potential, and the plurality of second electrodes supply a second electric potential different from the first electric potential. The plurality of first electrodes and the plurality of second electrodes are disposed alternately in both a row direction and a column direction, in a central part of the chip body. The plurality of wirings include a plurality of first wirings and a plurality of second wirings.

Abstract: A semiconductor structure including a substrate, a dielectric layer and a polysilicon layer is provided. The dielectric layer is disposed on the substrate. The polysilicon layer is disposed on the dielectric layer. A fluorine dopant concentration in the polysilicon layer presents Gaussian distributions from a top portion to a bottom portion of the polysilicon layer. Fluorine dopant peak concentrations of the Gaussian distributions are progressively decreased from the top portion to the bottom portion of the polysilicon layer.

Abstract: A method for forming metal contacts within a semiconductor device includes forming a first-layer contact into a first dielectric layer that surrounds at least one gate electrode, the first-layer contact extending to a doped region of an underlying substrate. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second-layer contact extending through the second dielectric layer to the first-layer contact.

Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.