Abstract: A photodetection device includes: a photoelectric converter generating charge; a first diffusion region having a first end connected to the photoelectric converter and a second end and extending in a first direction from the first end toward the second end; a second diffusion region having a third end connected to a first side surface, of the first diffusion region, which is along the first direction and a fourth end and extending in a second direction from the third end toward the fourth end; a first charge accumulator connected to the fourth end; a first gate electrode covering at least part of the first diffusion region; and a second gate electrode covering at least part of the second diffusion region. The second gate electrode covers a first portion of the first diffusion region without the first gate electrode intervention. The first portion is adjacent to the second diffusion region.

Abstract: A bipolar transistor is described. In accordance with one aspect of the present invention the bipolar transistor comprises a semiconductor body including a collector region and a base region arranged on top of the collector region. The base region has a first crystalline structure and is at least partly doped with dopants of a first doping type. The collector region is laterally enclosed by a trench isolation and is doped with dopants of a second doping type. The transistor further comprises a conductive base contact layer laterally enclosing the base region which is doped with dopants of the first doping type. The base contact layer comprises a part with the first crystalline structure and a part with a second crystalline structure, wherein the part with the second crystalline structure laterally encloses the part with the first crystalline structure.

Abstract: The present disclosure relates to an OLED panel, manufacturing method thereof, and a display device. The method for manufacturing an OLED panel comprises: forming an auxiliary electrode layer on a substrate, and forming a morphological transformation layer on the auxiliary electrode layer; forming an organic functional layer, wherein the organic functional layer covers the morphological transformation layer; removing the morphological transformation layer and a part of the organic functional layer corresponding to the morphological transformation layer from the auxiliary electrode layer; and forming a cathode layer on the organic functional layer and the auxiliary electrode layer.

Abstract: A display device includes a substrate having flexibility, a transistor having a gate insulating film and further having a semiconductor layer and a gate electrode that sandwich the gate insulating film, the transistor formed in an area where the substrate is bent, and a gate wiring line so formed on the substrate as to be connected to the gate electrode, and the gate electrode has an area that is present in an area where the gate electrode overlaps with the semiconductor layer and is thinner than at least part of the gate wiring line.

Abstract: A method of manufacturing an array substrate is provided. The method divides an array substrate into a curing area and a stretchable area. A metal wiring corresponding to the stretchable area is made of a flexible conductive material, so as to reduce disconnection risk of the display panel during bending.

Abstract: A new architecture to fabricate high-rise fully monolithic three-dimensional Integrated-Circuits (3D-ICs) is described. It has the major advantage over all known prior arts in that it substantially reduces RC-delays and fully eliminates or very substantially reduces the large and bulky electrically conductive Through-Silicon-VIAS in a monolithic 3D integration. This enables the 3D-ICs to have faster operational speed with denser device integration.

Abstract: The present technology relates to a semiconductor device and a method of manufacturing the semiconductor device capable of suppressing warpage of the semiconductor device. A mold release agent 101 is applied to a side surface of an upper chip 11. According to this, when a sealing resin 31 for protecting a bump 21 is applied, the bump 21 between the upper chip 11 and a lower chip 12 is protected and a fillet-shaped protruding portion does not adhere to the side surface of the upper chip 11 due to the mold release agent 101, so that a gap 111 is formed. According to this, a stress to warp the lower chip 12 is not generated even when contraction associated with drying of the sealing resin 31 between the side surface of the upper chip 11 and an upper surface of the lower chip 12 occurs, so that it becomes possible to suppress the warpage. The present technology may be applied to the semiconductor device.

Abstract: The present invention provides a method of manufacturing a semiconductor device to improve the manufacturing yield of the semiconductor device. The manufacturing method includes the steps of: forming a groove extending in a first direction (y direction) across a first power transistor formation region and a second power transistor formation region, in a back surface of a semiconductor wafer; filling the groove with a conductor film by forming the conductor film on the back surface in which the groove is formed; and exposing the back surface of the semiconductor wafer by removing a portion of the conductor film.

Abstract: A light emitting device includes a light emitting diode (“LED”), a first luminescent material that is configured to emit light having an emission peak in a green wavelength range, and a second luminescent material that is configured to emit narrow-spectrum light having an emission peak in an orange wavelength range. A light output of the light emitting device, which includes a portion of the light emitted by the LED, the light having the emission peak in the green wavelength range, and the light having the emission peak in the orange wavelength range, provides an appearance of white light. Related devices are also discussed.

Abstract: An organic photoelectric conversion element includes an anode, a cathode, and a photoelectric conversion portion between the anode and the cathode. The photoelectric conversion portion includes a first organic compound layer containing an organic compound. Also, a second organic compound layer is disposed between the cathode and the photoelectric conversion portion. The second organic compound layer contains an organic compound having an ionization potential of 5.1 eV or less and a band gap of 2.5 eV or more.

Abstract: In a semiconductor device including a low lifetime region of a depth within a range on both sides sandwiching a p-n junction of a p-type semiconductor region bottom portion, the low lifetime region includes a central region that has a portion coinciding with the semiconductor region as seen from one main surface side and is selectively formed as far as the position of a contact end portion of a region of the coinciding portion with which the semiconductor region and a metal electrode are in contact, a peripheral region wherein the central region extends as far as the position of an outer peripheral end of the semiconductor region, and an expanded end portion region wherein the peripheral region extends as far as an outer peripheral end of the innermost of guard rings. Because of this, it is possible to reduce leakage current while maintaining high reverse recovery current resistance.

Abstract: A MEMS sensor including a housing defining an interior and an inlet in fluid communication with an environment for sensing, a sensing die coupled to the housing for generating a signal based on the environment, an encapsulant is applied to the sensing die to protect the sensing die without interfering with the operation of the sensing die, characterized in that the encapsulant is a composition of a non-crosslinked substance having an organic backbone, and a silica thickener.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first III-V compound layer over the substrate, a second III-V compound layer on the first III-V compound layer, a third III-V compound layer on the second III-V compound layer, a source region on the third III-V compound layer, and a drain region on the third III-V compound layer. A percentage of aluminum of the third III-V compound layer is greater than that of the second III-V compound layer.

Abstract: Various embodiments provide for a chip package including a carrier; a layer over the carrier; a further carrier material over the layer, the further carrier material comprising a foil; one or more openings in the further carrier material, wherein the one or more openings expose at least one or more portions of the layer from the further carrier material; and a chip comprising one or more contact pads, wherein the chip is adhered to the carrier via the one or more exposed portions of the layer.

Abstract: An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes an insulating substrate, a semiconductor chip, a plate member, and a cooler. The insulating substrate includes insulating ceramics serving as an insulating plate, and conductive plates provided on opposite surfaces of the insulating ceramics. The semiconductor chip is provided on an upper surface of the insulating substrate. The plate member is bonded to a lower surface of the insulating substrate. The cooler is bonded to a lower surface of the plate member. At least one of bonding between a lower surface of the insulating substrate and the plate member and bonding between a lower surface of the plate member and the cooler is performed via a bonding member composed mainly of tin. Also, a cyclic stress of the plate member is smaller than a tensile strength of the bonding member.

Abstract: A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material.

Abstract: A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.

Abstract: Guard ring technology is disclosed. In one example, an electronic component guard ring can include a barrier having a first barrier portion and a second barrier portion oriented end to end to block ion diffusion and crack propagation in an electronic component. The guard ring can also include an opening in the barrier between the first and second barrier portions extending between a first side and a second side of the barrier. Associated systems and methods are also disclosed.

Abstract: A display device according to an exemplary embodiment includes: a thin film transistor array panel; and a color conversion display panel overlapping the thin film transistor array panel, the color conversion display panel including: a substrate; a color conversion layer positioned between the substrate and the thin film transistor array panel and including a semiconductor nanocrystal; a transparent layer positioned between the substrate and the thin film transistor array panel; and at least one of a first buffer layer positioned between the color conversion layer and the substrate and between the transparent layer and the substrate, and a second buffer layer positioned between the color conversion layer and the thin film transistor array panel and between the transparent layer and the thin film transistor array panel, and at least one of the first buffer layer and the second buffer layer includes a porous layer.