Abstract: A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, a plurality of wirings, and a solder resist layer, in which the plurality of wirings and the solder resist layer are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the plurality of wirings, and has an aperture on each of the plurality of wirings. The plurality of solder-including electrodes include at least one gap control electrode. The at least one gap control electrode includes a columnar metal layer and a solder layer in order named from side on which the chip body is disposed, and includes an overlap region where the columnar metal layer and the solder resist layer overlap each other, along part or all of an aperture end of the aperture.

Abstract: An array substrate and a display panel are provided. The array substrate includes a base layer, a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, a first electrode layer, and a reflective layer successively stacked along a direction perpendicular to a plane in which the base layer is located. The second metal layer is used to form a source and a drain of a thin film transistor. The first electrode layer is used to form a pixel electrode. The second insulating layer is provided with a through-hole. The pixel electrode is connected to the drain of the thin film transistor through the through-hole. The reflective layer is provided with a first through-hole, and an orthographic projection of the first through-hole onto the base layer covers an orthographic projection of the through-hole onto the base layer.

Abstract: An image sensor with high quantum efficiency is provided. In some embodiments, a semiconductor substrate includes a non-porous semiconductor layer along a front side of the semiconductor substrate. A periodic structure is along a back side of the semiconductor substrate. A high absorption layer lines the periodic structure on the back side of the semiconductor substrate. The high absorption layer is a semiconductor material with an energy bandgap less than that of the non-porous semiconductor layer. A photodetector is in the semiconductor substrate and the high absorption layer. A method for manufacturing the image sensor is also provided.

Abstract: An object of an embodiment of the present invention is to manufacture a semiconductor device with high display quality and high reliability, which includes a pixel portion and a driver circuit portion capable of high-speed operation over one substrate, using transistors having favorable electric characteristics and high reliability as switching elements. Two kinds of transistors, in each of which an oxide semiconductor layer including a crystalline region on one surface side is used as an active layer, are formed in a driver circuit portion and a pixel portion. Electric characteristics of the transistors can be selected by choosing the position of the gate electrode layer which determines the position of the channel. Thus, a semiconductor device including a driver circuit portion capable of high-speed operation and a pixel portion over one substrate can be manufactured.

Abstract: A vertical field-effect transistor (FET) device includes a monolithically integrated bypass diode connected between a source contact and a drain contact of the vertical FET device. According to one embodiment, the vertical FET device includes a pair of junction implants separated by a junction field-effect transistor (JFET) region. At least one of the junction implants of the vertical FET device includes a deep well region that is shared with the integrated bypass diode, such that the shared deep well region functions as both a source junction in the vertical FET device and a junction barrier region in the integrated bypass diode. The vertical FET device and the integrated bypass diode may include a substrate, a drift layer over the substrate, and a spreading layer over the drift layer, such that the junction implants of the vertical FET device are formed in the spreading layer.

Abstract: The present disclosure relates to a solid-state image capturing element capable of suppressing a dark current, a manufacturing method thereof, and an electronic device. Provided is a solid-state image capturing element including: a photoelectric conversion unit formed outside a semiconductor substrate; and a charge retention section that is formed in the semiconductor substrate and retains charges generated in the photoelectric conversion unit. Among surfaces of the charge retention section, a bottom surface on a side opposite to a surface of a gate side of a transistor formed in the semiconductor substrate is covered by an insulation film. The present disclosure can be applied to, for example, solid-state image capturing elements and the like.

Abstract: An optoelectronic device with a multi-layer contact is described. The optoelectronic device can include an n-type semiconductor layer having a surface. A mesa can be located over a first portion of the surface of the n-type semiconductor layer and have a mesa boundary. An n-type contact region can be located over a second portion of the surface of the n-type semiconductor contact layer entirely distinct from the first portion, and be at least partially defined by the mesa boundary. A first n-type metallic contact layer can be located over at least a portion of the n-type contact region in proximity of the mesa boundary, where the first n-type metallic contact layer forms an ohmic contact with the n-type semiconductor layer. A second metallic contact layer can be located over a second portion of the n-type contact region, where the second metallic contact layer is formed of a reflective metallic material.

Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to electrical contacts to a transistor device, and a method of making such electrical contacts. In one aspect, a method of forming one or more self-aligned gate contacts in a semiconductor device includes providing a substrate having formed thereon at least one gate stack, where the gate stack includes a gate dielectric and a gate electrode formed over an active region in or on the substrate, and where the substrate further has formed thereon a spacer material coating lateral sides of the at least one gate stack. The method additionally includes selectively recessing the gate electrode of the at least one gate stack against the spacer material, thereby creating a first set of recess cavities. The method additionally includes filling the first set of recess cavities with a dielectric material gate cap.

Abstract: A semiconductor package can include a substrate and a semiconductor chip on the substrate. A first molding portion can cover the semiconductor chip and can include a first sidewall and a second sidewall opposite each other. A second molding portion can extend on the substrate along the first sidewall and along the second sidewall, where the first molding portion can include a nonconductive material, and the second molding portion can include a conductive material.

Abstract: A switch fabrication method can include forming a plurality of elements, and connecting the elements in series between a first terminal and a second terminal, such that the elements include a first end element connected to the first terminal and a second end element connected to the second terminal. Each element can have a parameter such that the elements have a distribution of parameter values that decreases from the first end element for at least half of the elements to a minimum parameter value corresponding to an element between the first end element and the second end element. The minimum parameter value can be less than the parameter value of the second end element, and the parameter value of the first end element can be greater than or equal to the parameter value of the second end element.

Abstract: One embodiment relates to an organic electronic material containing a charge transport polymer or oligomer, wherein the charge transport polymer or oligomer has a structural unit containing an aromatic amine structure substituted with a fluorine atom.

Abstract: A semiconductor package includes a core member having a cavity penetrating through first and second surfaces, a semiconductor chip disposed in the cavity and having an active surface having connection, a passive component module disposed in the cavity, including a plurality of passive components and a resin portion encapsulating the plurality of passive components, and having a mounting surface from which connection terminals of the passive components are exposed, a connection member on the second surface and including a redistribution layer connected to the connection pads of the semiconductor chip and connection terminals of some of the plurality of passive components, connection terminals of the others of the plurality of passive components not being connected to the redistribution layer.

Abstract: A semiconductor structure is provided that includes a bulk semiconductor substrate of a first semiconductor material. The structure further includes a plurality of fin pedestal structures of a second semiconductor material located on the bulk semiconductor substrate of the first semiconductor material, wherein the second semiconductor material is different from the first semiconductor material. In accordance with the present application, each fin pedestal structure includes a pair of spaced apart semiconductor fins of the second semiconductor material.

Abstract: A method for manufacturing a semiconductor device includes forming a hardmask layer on a substrate, patterning the hardmask layer to form a plurality of patterned hardmask portions on the substrate, depositing a dummy hardmask layer on the substrate, patterning the dummy hardmask layer to form a plurality of patterned dummy hardmask portions on the substrate, wherein each of the plurality of patterned dummy hardmask portions is positioned adjacent respective outermost patterned hardmask portions of the plurality of patterned hardmask portions, and transferring a pattern of the plurality of patterned hardmask portions and the plurality of patterned dummy hardmask portions to the substrate to form a plurality of fins and a plurality of dummy fins from the substrate.

Abstract: A magnetoresistive random access memory device (MRAM) device is described. The MRAM device has a stack arrangement in which a tunnel barrier layer is formed over a magnetizable reference layer, a metal layer is formed over the tunnel barrier layer, a free layer of a magnetizable material is formed over the metal layer, and an oxide layer is formed over the free layer as a cap layer. The resulting MRAM device has a thin free layer that exhibits a low magnetic moment.

Abstract: A packaged semiconductor device has a conductive film that covers a first major surface and surrounding side surfaces of an integrated circuit die. The conductive film provides five-sided shielding of the integrated circuit die. A metal heat sink may be attached to an exposed major surface of the conductive film for dissipating heat generated by the die.

Abstract: The present technology relates to an imaging element, an imaging device, and a manufacturing apparatus and a method that facilitate electric charge transfer. An imaging element of the present technology includes a vertical transistor that has a potential with a gradient in at least part of a charge transfer channel that transfers electric charge of a photoelectric conversion unit. Also, an imaging device of the present technology includes: an imaging element including a vertical transistor that has a potential with a gradient in at least part of a charge transfer channel that transfers electric charge of a photoelectric conversion unit; and an image processing unit that performs image processing on captured image data obtained by the imaging element.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first dielectric layer over a first substrate, and the dielectric layer has a plurality of openings. The method also includes forming a first graphene layer in the openings and over the first dielectric layer, and forming an insulating layer in the first graphene layer. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second graphene layer in and over the second dielectric layer. A portion of the second graphene layer interfaces with a portion of the first graphene layer.

Abstract: Examples of a package for a flange mount device are described. In one example, the package includes a thermally conductive base, a base substrate, and a lid having a cavity. The base substrate includes a through hole and radio frequency (RF) input, RF output, and bias traces that extend to a perimeter of the through hole. The lid includes a cavity and RF input coupling, RF output coupling, and bias coupling traces. A device can be secured to the thermally conductive base, and the lid can be secured to the thermally conductive base, with the base substrate secured between the lid and the thermally conductive base, coupling the traces of the base substrate to the traces of the lid. Other components, such as biasing, blocking, and bypassing components can be easily integrated into the package. Impedance matching and electromagnetic shielding components can also be easily integrated into the package.

Abstract: An array substrate and a display device are provided. The array substrate includes a base substrate, and a first conductive layer and a second conductive layer which are sequentially disposed on the base substrate, and at least two passivation layers are continuously arranged between the first conductive layer and the second conductive layer in a direction perpendicular to the base substrate.